17:20:17 (lmgrd) -----------------------------------------------
17:20:17 (lmgrd)   Please Note:
17:20:17 (lmgrd) 
17:20:17 (lmgrd)   This log is intended for debug purposes only.
17:20:17 (lmgrd)   There are many details in licensing policies
17:20:17 (lmgrd)   that are not reported in the information logged
17:20:17 (lmgrd)   here, so if you use this log file for any kind
17:20:17 (lmgrd)   of usage reporting you will generally produce
17:20:17 (lmgrd)   incorrect results.
17:20:17 (lmgrd) 
17:20:17 (lmgrd) -----------------------------------------------
17:20:17 (lmgrd) 
17:20:17 (lmgrd) 
17:20:17 (lmgrd) lmgrd running as root:
17:20:17 (lmgrd) 	This is a potential security problem
17:20:17 (lmgrd) 	And is not recommended
17:20:17 (lmgrd) FLEXlm (v8.4a) started on localhost.localdomain (linux) (4/1/2007)
17:20:17 (lmgrd) Copyright (c) 1988-2003 by Macrovision Corporation. All rights reserved.
17:20:17 (lmgrd) US Patents 5,390,297 and 5,671,412.
17:20:17 (lmgrd) World Wide Web:  http://www.macrovision.com
17:20:17 (lmgrd) License file(s): /Cadence/share/license/cadence.dat 
17:20:17 (lmgrd) lmgrd tcp-port 5280
17:20:17 (lmgrd) Starting vendor daemons ... 
17:20:17 (lmgrd) Started cdslmd (internet tcp_port 32770 pid 3080)
17:20:18 (cdslmd) FLEXlm version 0.0(null)
17:20:18 (cdslmd) Server started on localhost.localdomain for:	100		
17:20:18 (cdslmd) 111		11400		12141		
17:20:18 (cdslmd) 12500		14000		14010		
17:20:18 (cdslmd) 14020		14040		14101		
17:20:18 (cdslmd) 14111		14120		14130		
17:20:18 (cdslmd) 14140		14410		200		
17:20:18 (cdslmd) 20120		20121		20122		
17:20:18 (cdslmd) 20123		20124		20127		
17:20:18 (cdslmd) 20128		20220		20221		
17:20:18 (cdslmd) 20222		20227		206		
17:20:18 (cdslmd) 207		21060		21200		
17:20:18 (cdslmd) 21400		21900		21920		
17:20:18 (cdslmd) 22650		22800		22810		
17:20:18 (cdslmd) 24015		24025		24100		
17:20:18 (cdslmd) 24205		250		251		
17:20:18 (cdslmd) 26000		274		276		
17:20:18 (cdslmd) 279		283		300		
17:20:18 (cdslmd) 305		312		314		
17:20:18 (cdslmd) 316		318		32110		
17:20:18 (cdslmd) 32140		32150		32190		
17:20:18 (cdslmd) 322		32500		32501		
17:20:18 (cdslmd) 32502		32510		32550		
17:20:18 (cdslmd) 32600		32610		32620		
17:20:18 (cdslmd) 32630		32640		32760		
17:20:18 (cdslmd) 33010		33301		334		
17:20:18 (cdslmd) 336		34500		34510		
17:20:18 (cdslmd) 365		370		371		
17:20:18 (cdslmd) 37100		373		40020		
17:20:18 (cdslmd) 40030		40040		40500		
17:20:18 (cdslmd) 41000		50000		50010		
17:20:18 (cdslmd) 501		50110		50200		
17:20:18 (cdslmd) 51022		51023		51060		
17:20:18 (cdslmd) 51070		51170		550		
17:20:18 (cdslmd) 570		61300		61400		
17:20:18 (cdslmd) 920		940		945		
17:20:18 (cdslmd) 950		960		963		
17:20:18 (cdslmd) 964		965		966		
17:20:18 (cdslmd) 972		974		991		
17:20:18 (cdslmd) 994		995		A2dxf		
17:20:18 (cdslmd) A2dxf		ABIT		ADV_6SUPUC_ALL	
17:20:18 (cdslmd) ALL_EBD		AMD_MACH	ANALOG_WORKBENCH 
17:20:18 (cdslmd) APD		AWB_BEHAVIOR	AWB_Batch	
17:20:18 (cdslmd) AWB_DIST_SIM	AWB_MAGAZINE	AWB_MAGNETICS	
17:20:18 (cdslmd) AWB_MIX		AWB_PPLOT	AWB_RESOLVE_OPT 
17:20:18 (cdslmd) AWB_SIMULATOR	AWB_SMOKE	AWB_SPICEPLUS	
17:20:18 (cdslmd) AWB_STATS	Actel_FPGA	Advanced_Cell_Placer 
17:20:18 (cdslmd) Advanced_Package_Designer Advanced_Package_Designer Affirma_AMS_distrib_processing 
17:20:18 (cdslmd) Affirma_NC_Simulator Affirma_RF_IC_package Affirma_RF_SPW_model_link 
17:20:18 (cdslmd) Affirma_sim_analysis_env Affirma_transaction_analysis Allegro_CAD_Interface 
17:20:18 (cdslmd) Allegro_Designer Allegro_Expert	Allegro_Librarian 
17:20:18 (cdslmd) Allegro_PCB	Allegro_PCB_Interface Allegro_Studio	
17:20:18 (cdslmd) Allegro_Studio	Allegro_Symbol	Allegro_Symbol	
17:20:18 (cdslmd) Allegro_Viewer_Plus Allegro_design_expert Allegro_designer_suite 
17:20:18 (cdslmd) Allegro_performance Altera_MAX	Artist_Optimizer 
17:20:18 (cdslmd) Artist_Statistics Atmel_ATV	BOGUS		
17:20:18 (cdslmd) Base_Digital_Body_Lib Base_Verilog_Lib BlockMaster_Characterizer 
17:20:18 (cdslmd) BlockMaster_Optimizer BoardQuest_Designer BoardQuest_Team 
17:20:18 (cdslmd) CELL3		CELL3_ARO	CELL3_CROSSTALK 
17:20:18 (cdslmd) CELL3_CTS	CELL3_ECL	CELL3_OPENDEV	
17:20:18 (cdslmd) CELL3_OPENEXE	CELL3_PA	CELL3_PR	
17:20:18 (cdslmd) CELL3_QPLACE_TIMING CELL3_SCAN	CELL3_TIMING	
17:20:18 (cdslmd) CELL3_WIDEWIRE	CHDL_DesignAccess CP_Ele_Checks	
17:20:18 (cdslmd) CPtoolkit	CWAVES		CWB01		
17:20:18 (cdslmd) CWB03		CWB04		CWB05		
17:20:18 (cdslmd) Capture		CaptureCIS	Capture_CIS_Studio 
17:20:18 (cdslmd) CheckADV_ALL	CheckPlus	Checkplus_Expert 
17:20:18 (cdslmd) Clock_Tree_Generation Cobra_Simulator ComposerCheckPlus_AdvRules 
17:20:18 (cdslmd) ComposerCheckPlus_Checker ComposerCheckPlus_RuleDev Composer_EDIF300_Connectivity 
17:20:18 (cdslmd) Composer_EDIF300_Schematic Composer_Spectre_Sim_Solution ConcICe_Option	
17:20:18 (cdslmd) ConceptHDL	Concept_HDL_expert Concept_HDL_rules_checker 
17:20:18 (cdslmd) Concept_HDL_studio Corners_Analysis DFM_6SUPUC_ALL	
17:20:18 (cdslmd) DISCRETE_LIB	DRAC2CORE	DRAC2DRC	
17:20:18 (cdslmd) DRAC2LVS	DRAC3CORE	DRAC3DRC	
17:20:18 (cdslmd) DRAC3LVS	DRACACCESS	DRACDIST	
17:20:18 (cdslmd) DRACERC		DRACLPE		DRACLVS		
17:20:18 (cdslmd) DRACPG_E	DRACPLOT	DRACPRE		
17:20:18 (cdslmd) DRACSLAVE	Datapath_Preview_Option Datapath_VHDL	
17:20:18 (cdslmd) Datapath_Verilog Device_Level_Placer Device_Level_Router 
17:20:18 (cdslmd) Distributed_Dracula_Option EBD_edit	EBD_floorplan	
17:20:18 (cdslmd) EBD_power	EB_6SUPUC_ALL	EDIF_Netlist_Interface 
17:20:18 (cdslmd) EDIF_Schematic_Interface EMCdisplay	EMControl	
17:20:18 (cdslmd) EMControl_Float EMI_ALL		EditBase_ALL	
17:20:18 (cdslmd) EditFST_ALL	EditPlace_ALL	EditRoute_ALL	
17:20:18 (cdslmd) Envisia_GE_ultra_place_route Envisia_SE_ultra_place_route Express		
17:20:18 (cdslmd) ExpressPlus	Extended_Digital_Body_Lib Extended_Digital_Lib 
17:20:18 (cdslmd) Extended_Verilog_Lib FPGA_Flows	FPGA_OPTIMIZER	
17:20:18 (cdslmd) FPGA_Tools	FST_6SUPUC_ALL	FUNCTION_LIB	
17:20:18 (cdslmd) FloatPC_ALL	Framework	GATEENSEMBLE	
17:20:18 (cdslmd) GATEENSEMBLE_ARO GATEENSEMBLE_CROSSTALK GATEENSEMBLE_CTS 
17:20:18 (cdslmd) GATEENSEMBLE_CTS_LE GATEENSEMBLE_CTS_UL GATEENSEMBLE_ECL 
17:20:18 (cdslmd) GATEENSEMBLE_LOWEND GATEENSEMBLE_OPENDEV GATEENSEMBLE_OPENEXE 
17:20:18 (cdslmd) GATEENSEMBLE_PA GATEENSEMBLE_PR_LE GATEENSEMBLE_PR_UL 
17:20:18 (cdslmd) GATEENSEMBLE_QPLACE_TIMING GATEENSEMBLE_SCAN GATEENSEMBLE_TIMING 
17:20:18 (cdslmd) GATEENSEMBLE_TIMING_LE GATEENSEMBLE_TIMING_UL GATEENSEMBLE_UNLIMITED 
17:20:18 (cdslmd) GATEENSEMBLE_WIDEWIRE Gate_Ensemble_DSM Gate_Ensemble_DSM_Crosstalk 
17:20:18 (cdslmd) Gate_Ensemble_WARP HDL-DESKTOP	HYB_6SUPUC_ALL	
17:20:18 (cdslmd) IC_Inspector	IC_InspectorEngr_ALL IC_Inspector_ALL 
17:20:18 (cdslmd) IC_autoroute	IC_autoroute_ALL IC_devicegen_ALL 
17:20:18 (cdslmd) IC_deviceplace_ALL IC_edit		IC_edit_ALL	
17:20:18 (cdslmd) IC_editfast_ALL IC_gcell_route_ALL IC_hsrules	
17:20:18 (cdslmd) IC_hsrules_ALL	IC_mp_route_ALL IC_power_route_ALL 
17:20:18 (cdslmd) IDF_Bi_Directional_Interface IPlaceBase_ALL	Intrica_powerplane_builder 
17:20:18 (cdslmd) LAS_Cell_Optimization LEAPFROG-BV	LEAPFROG-CV	
17:20:18 (cdslmd) LEAPFROG-SLAVE	LEAPFROG-SV	LEAPFROG-SYS	
17:20:18 (cdslmd) LID10		LID11		LINEAR_LIB	
17:20:18 (cdslmd) LSE		Layout		LayoutEE	
17:20:18 (cdslmd) LayoutPlus	MAG_LIB		MIXAD_LIB	
17:20:18 (cdslmd) NC_VHDL_Simulator NC_Verilog_Compiler NC_Verilog_Data_Prep_Compiler 
17:20:18 (cdslmd) NC_Verilog_Simulator Nihongoconcept	OASIS_Simulation_Interface 
17:20:18 (cdslmd) OpenModeler	OpenModeler_SFI OpenModeler_SWIFT 
17:20:18 (cdslmd) OpenSim		OpenWaves	Optimizer	
17:20:18 (cdslmd) OrCAD		PB_6SUPUC_ALL	PB_USUPUC_ALL	
17:20:18 (cdslmd) PCB_design_expert PCB_design_studio PCB_designer	
17:20:18 (cdslmd) PCB_librarian_expert PCB_studio_variants PE_Librarian	
17:20:18 (cdslmd) PICDesigner	PIC_Utilities	PLD		
17:20:18 (cdslmd) PPRoute_ALL	PSpice		PSpiceAD	
17:20:18 (cdslmd) PSpiceBasics	PWM_LIB		Pearl		
17:20:18 (cdslmd) Pearl_Cell	PlaceBase_ALL	PlaceOrIPlace_ALL 
17:20:18 (cdslmd) Placement_Based_Synthesis Prevail_Board_Designer Prevail_Correct_By_Design 
17:20:18 (cdslmd) Prevail_Designer Preview_Synopsys_Interface QPlace		
17:20:18 (cdslmd) Quickturn_Model_Manager RB_6SUPUC	RB_6SUPUC_ALL	
17:20:18 (cdslmd) RapidPART	RouteADV	RouteADV_ALL	
17:20:18 (cdslmd) RouteBase	RouteBase_ALL	RouteDF		
17:20:18 (cdslmd) RouteDFM_ALL	RouteFST	RouteFST_ALL	
17:20:18 (cdslmd) RouteHYB_ALL	RouteMVIA_ALL	RouteMin_ALL	
17:20:18 (cdslmd) RouteOrEdit_ALL SPECCTRAQuest	SPECCTRAQuest_Planner 
17:20:18 (cdslmd) SPECCTRAQuest_SI_expert SPECCTRAQuest_signal_expert SPECCTRAQuest_signal_explorer 
17:20:18 (cdslmd) SPECCTRA_PCB	SPECCTRA_autoroute SPECCTRA_designer 
17:20:18 (cdslmd) SPECCTRA_expert SPECCTRA_expert_system SPECCTRA_performance 
17:20:18 (cdslmd) SQ_Digital_Logic_SI_Lib SQ_FPGA_SI_Lib	SQ_Memory_SI_Lib 
17:20:18 (cdslmd) SQ_Microprocessor_SI_Lib SWIFT		Schematic_Generator 
17:20:18 (cdslmd) SigNoise	SigNoise	SigNoiseCS	
17:20:18 (cdslmd) SigNoiseEngineer SigNoiseExpert	SigNoiseStdDigLib 
17:20:18 (cdslmd) SigNoise_Float	Signal_Integrity Sigxp		
17:20:18 (cdslmd) Sigxp_tier	Sigxp_tier_EXPERT SiliconQuest	
17:20:18 (cdslmd) SiliconQuest_CTGen_Option Silicon_Ensemble Silicon_Ensemble_CTS 
17:20:18 (cdslmd) Silicon_Ensemble_DSM Silicon_Ensemble_DSM_Crosstalk Silicon_Ensemble_OpenDev 
17:20:18 (cdslmd) Silicon_Ensemble_OpenExe Silicon_Ensemble_WARP Silicon_Synthesis_QPBS 
17:20:18 (cdslmd) SimVision	SpectreBasic	SpectreRF	
17:20:18 (cdslmd) Spectre_BTAHVMOS_Models Spectre_BTASOI_Models Spectre_NorTel_Models 
17:20:18 (cdslmd) Spectre_ST_Models StudioPSpiceAD	Substrate_Coupling_Analysis 
17:20:18 (cdslmd) Synlink_Interface UET		ULMdelta	
17:20:18 (cdslmd) ULMecho		ULMhotel	ULMindia	
17:20:18 (cdslmd) ULMjuliette	ULMmike		Universal_Smartpath 
17:20:18 (cdslmd) VB_6SUPUC	VB_6SUPUC_ALL	VB_USUPUC_ALL	
17:20:18 (cdslmd) VERILOG-SLAVE	VERILOG-XL	VERITIME	
17:20:18 (cdslmd) VHDLLink	VXL-ALPHA	VXL-LMC-HW-IF	
17:20:18 (cdslmd) VXL-SWITCH-RC	VXL-TURBO	VXL-VCW		
17:20:18 (cdslmd) VXL-VET		VXL-VLS		VXL-VRA		
17:20:18 (cdslmd) Vampire_HDRC	Vampire_HLVS	Vampire_MP	
17:20:18 (cdslmd) Vampire_RCX	Vampire_UI	Verillog_XL_Turbo_NT 
17:20:18 (cdslmd) ViewBase	ViewBaseEngr_ALL ViewBase_ALL	
17:20:18 (cdslmd) Virtuoso_Schem_Option Virtuoso_XL	Xilinx_FPGA	
17:20:18 (cdslmd) actomd		adv_package_designer_expert adv_package_engineer_expert 
17:20:18 (cdslmd) allegro_dfa	allegro_dfa_att allegro_non_partner 
17:20:18 (cdslmd) allegroprance	archiver	arouter		
17:20:18 (cdslmd) caeviews	cals_out	catia		
17:20:18 (cdslmd) cbds_in		cdxe_in		comp		
17:20:18 (cdslmd) compose		compose_autoplan compose_gcr	
17:20:18 (cdslmd) compose_scells	compose_tlmr	compose_util	
17:20:18 (cdslmd) concept		conceptXPC	cpe		
17:20:18 (cdslmd) cpte		crefer		cvtomd		
17:20:18 (cdslmd) debug		dfsverifault	dracula_in	
17:20:18 (cdslmd) dxf2a		e2v		eCapture	
17:20:18 (cdslmd) edif2ged	expert		expgen		
17:20:18 (cdslmd) explorer	fethman		fetsetup	
17:20:18 (cdslmd) fluke		fsim		gbom		
17:20:18 (cdslmd) ged2edif	glib		gloss		
17:20:18 (cdslmd) gphysdly	gscald		gspares		
17:20:18 (cdslmd) hp3070		iges_electrical intrgloss	
17:20:18 (cdslmd) intrroute	intrsignoise	ipc_in		
17:20:18 (cdslmd) ipc_out		lwb		mdin		
17:20:18 (cdslmd) mdout		mdtoac		mdtocv		
17:20:18 (cdslmd) multiwire	packager	pcb_editor	
17:20:18 (cdslmd) pcb_engineer	pcb_interactive pcb_prep	
17:20:18 (cdslmd) pcb_review	pcomp		placement	
17:20:18 (cdslmd) plotVersa	ptc_in		ptc_out		
17:20:18 (cdslmd) quanticout	rapidsim	realchiplm	
17:20:18 (cdslmd) redifnet	rt		sdrc_in		
17:20:18 (cdslmd) sdrc_out	shapefill	signal_explorer 
17:20:18 (cdslmd) sigxp_explorer	skillDev	stream_in	
17:20:18 (cdslmd) stream_out	swap		sx		
17:20:18 (cdslmd) synSmartIF	synSmartLib	synTiOpt	
17:20:18 (cdslmd) tsTSynVHDL	tsTSynVLOG	tsTestGen	
17:20:18 (cdslmd) tsTestIntf	tscr		tune		
17:20:18 (cdslmd) tw01		tw02		v2e		
17:20:18 (cdslmd) verifault	vgen		viable		
17:20:18 (cdslmd) visula_in	vloglink	wedifsch	
17:20:18 (cdslmd) xilCds		xilComposerFE	xilConceptFE	
17:20:18 (cdslmd) xilEdif		
17:20:18 (cdslmd) 
17:20:18 (cdslmd) All FEATURE lines for this vendor behave like INCREMENT lines
17:20:18 (cdslmd) 
