;-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;-;                           ON Semiconductor
;-;	                  Technology Development Organization
;-;			Design Systems Technology - Design Kit Development - Roznov
;-;                                  
;-;
;-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;-;                 ON SEMICONDUCTOR CONFIDENTIAL PROPRIETARY
;-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;-;
;-; RCS:
;-; $Header$
;-; $Author$
;-; $Revision$
;-; $Date$
;-; $State$
;-; $Locker$
;-; $Source$
;-;
;-; Cadence version 4.4
;-;
;-; (C) Copyright 2000, ON Semiconductor, all rights reserved.
;-;
;-; File: 
;-; Language: Skill
;-;
;-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

printf( "executing simrc ... \n")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; generic variables
;
; Note that the name  "basic" is a logical or relative name. Don't type in
; a full Unix pathname to the library, just its normal 4.2 name. To actually
; find the library "basic", the system uses the library search path that may
; be defined in the file ".cdsinit".
;simNlpGlobalLibName  = "basic"

;Note: Analog Artist users should use the following:                        
;simNlpGlobalLibName  = "analogLib"

; The normal default for simTimeUnit is 1 nanosecond. For the GaCells 0.6 micro
; library, we'll use a simulation resolution of 10 picosecond for the parts.
; Note that this value (10.0e-12) must be consistent with the value used by
; your STL input.stl file (in the "deftiming" statement) and your library HDL
; description files (for proper operation of the SDF Annotator).
;simTimeUnit                 = 10.0e-12
;
; Using a 10ps internal precision for the Verilog simulator.
;simVerilogTimePrecisionVar  = simTimeUnit

;simCapUnit   = 1.0e-15
;simNlpGlobalBlock = "nlpglobals"

; simNetlistHier     = nil
; simCapFileDir      = "/tmp/test/sim.cap"
; simModelNamePrefix = "Model"

;simDoPostLayout      = t

; "simRetainFterms" is used with the "addDummy()" routine 
; in order to use Cell-Ensemble on a macro block.
;simRetainFterms = t

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for verilog
verilogSimViewList = '("behavioral" "functional" "verilog" "schematic" "cmos.sch" "symbol" )
verilogSimStopList = '("functional" "behavioral" "verilog" "symbol")
simVerilogPwrNetList = '("vddd!" "vdd!" "VDD!")
simVerilogGndNetList = '("gndd!" "gnd!" "GND!" "sub!")
simVerilogSimTimeValue = 1
simVerilogSimTimeUnit = "ps"
simVerilogSimPrecisionValue = 1
simVerilogSimPrecisionUnit = "ps"

when( getd('DstOnc25FindByName)
	  
	simVerilogInvocationOptionsFile = DstOnc25FindByName("verilogIncludeFiles.v" strcat("userSetup_" getShellEnvVar("USER") "/onc25"))
	simVerilogLibraryFile  =  DstOnc25FindByName("verilogOptions.v" strcat("userSetup_" getShellEnvVar("USER") "/onc25"))
	simVerilogLibraryDirectory = DstOnc25FindByName( "verilog" "models") || "" 
	
	printf("Choosing verilog control files :%L ,%L \n" simVerilogInvocationOptionsFile simVerilogLibraryFile)
	printf("Choosing verilog library path :%L \n" simVerilogLibraryDirectory)
)

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for hspice

hspiceSimViewList   = '("hspiceS" "cmos.sch" "device.sch" "schematic")
hspiceSimStopList   = '("hspiceS")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for spice

;spiceSimViewList   = '("device.sch" "cdsSpice" "schematic" "symbol")
;spiceSimStopList   = '("cdsSpice" "symbol")
;spiceSimStopList = '("spice.l6" "symbol")

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for TA timing analyzer

;taSimViewList   = '("ta.elc" "ta" "schematic" "symbol")
;taSimStopList   = '("ta.elc" "ta" "symbol")
; taSimStopList = '("ta.elc" "ta")
; for PRFlatten, used to generate autoLayout before Place & Route
;flattenSimViewList = '("abstract" "schematic"
;flattenSimStopList = '("abstract" "symbol")
; Will create a cellView called "autoLayout" when running PRFlatten.
;simFlatViewName  = "autoLayout"

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for lvs

lvsLimitLinesInOutFile = 5000

;;;;;;;;;;;;;;;;;;;;;;;
; for PDCompare or DIVA
; lvs       = control the depth of the netlisting
; extracted = useful for hierarchically-extracted reps
; abstract  = useful for ASIC P&R extraction
; symbol    = useful for custom layout extraction

;;;;;;;;;;;;;;;;;;;;;
; for transistor-level comparison
;lvsSchematicViewList = '( "lvs" "schematic" "gate.sch" "cmos.sch" )
;lvsLayoutViewList    = '( "lvs" "extracted" "schematic" "gate.sch" "cmos.sch" )
;lvsLayoutStopList    = '( "lvs" )
;lvsSchematicStopList = '( "lvs" )

;;;;;;;;;;;;;;;;;;;;
; for transistor-level comparison for analog artist                        

lvsSchematicViewList = '( "auLvs" "schematic" "cmos.sch" "device.sch"  )    
lvsLayoutViewList = '( "auLvs" "extracted" "schematic" )
lvsLayoutStopList    = '( "auLvs" )                                        
lvsSchematicStopList = '( "auLvs" )                                        

;;;;;;;;;;;;;;;;;;;;;
; for macro-cell comparison
; lvsSchematicViewList = '( "abstract" "schematic" "gate.sch" )
; lvsLayoutViewList    = '( "abstract" "extracted" )
; lvsLayoutStopList    = '( "abstract" )
; lvsSchematicStopList = '( "abstract" )

;;;;;;;;;;;;;;;;;;;;;;
; for symbolic checker
; lvsLayoutViewList    = '( "symlvs" "lvs" "schematic" "symbolic" )
; lvsSchematicViewList = '( "symlvs" "lvs" "schematic" "gate.sch" "cmos.sch" )
; lvsLayoutStopList    = '( "symlvs" "lvs" )
; lvsSchematicStopList = '( "symlvs" "lvs" )

;;;;;;;;;;;;;;;;;;;;;;                                                       
; for symbolic checker for analog artist                                     
; lvsLayoutViewList    = '( "symlvs" "auLvs" "schematic" "symbolic" )        
; lvsSchematicViewList = '( "symlvs" "auLvs" "schematic" "gate.sch" "cmos.sch" )
; lvsLayoutStopList    = '( "symlvs" "auLvs" )                               
; lvsSchematicStopList = '( "symlvs" "auLvs" )                               

;ercViewList = '( "lvs" "schematic" "gate.sch" "cmos.sch" )
;ercStopList = '( "lvs" )

;;;;;;;;;;;;;;;;;;;;;;                                                       
; for erc in analog artist                                                   
;ercViewList = '( "auLvs" "schematic" "gate.sch" "cmos.sch" )                  
;ercStopList = '( "auLvs" )                                                    


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for interactive simulation environment
; To run remote Verilog interactively, mount the /tmp directory of the remote
; machine to your local machine /remotetmp directory. In this file, set:
; iseRemoteDiskMountedAs = "/remotetmp"

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; for verilog

;simVerilogRestartSimulationFile = strcat(getWorkingDir() "/verilogInit.v")
;hnlVerilogCellAuxData = strcat(getWorkingDir() "/verilogInit.v")
;hnlVerilogGetAuxFilesToPwd = 't 

;*****************************************************************************
;initialization for netlister
;*****************************************************************************
;simVerilogFlattenBuses           = 'nil
;simVerilogLaiLmsiNetlisting      = 'nil
;simReNetlistAll                  = 't
;simVerilogNetlistExplicit        = 'nil
; The default top level module name and the instance name.
; simVerilogTopLevelModuleName = "test.top"

;*****************************************************************************\
;initialization for verilog command line arguments
;*****************************************************************************/
;verilogSimBinary                 = prependInstallPath( "bin/verilog.exe" )
; simVerilogPasswordFile           = prependInstallPath( "etc/license/verilog.vc" )
;simVerilogLibraryDirectory       = ""
;simVerilogLibraryFile            = ""
; Examples of posssible invocation options

;simVerilogInvocationOptions      = " -a -w +db +define+SYNTH +dlverbose +dslookc +laiexe +laidlddebug +libext+.v +maxdelays +max_err_count+5 +mconst +sdf_verbose +tms+ "

;simVerilogInteractiveCommandFile = ""
;simVerilogInvocationOptionsFile  = ""

; Post-layout simulation variables.
;
; The value "nil" of simVerilogDelayPrimitive means that the Cadence default 
; delay calculator used is $dcalc_path(..., "net.cap"). If the value is "t", the
; task dcalc_prim(..., "net.cap") will show up in the Run Directory
; file "delayTask.cmd".
;
; For delay paths to be back-annotated:
; Note 1: Cell ports are scalars.
; Note 2: Port names are the same as their net names.
; Note 3: No wired logic on a output port.
;
;simVerilogDelayPrimitive    = nil
; The report info goes into the file "si.out", and contains information
; on the interconnect nets.
;simVerilogDelayDetailReport = t
;simVerilogDelayUseDefault   = t


/*****************************************************************************\
 initialization for waveform display tool
\*****************************************************************************/
;simVerilogWavePackageVar         = "cWaves"


/*****************************************************************************\
 initialization for pld solution
\*****************************************************************************/
;   if( isDir( prependInstallPath( "etc/amAbel4" ) )
;   then
;     simVerilogLibraryFile = prependInstallPath( "etc/amAbel4/pldlib.v" )
;   )


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; .simrc for Veritime

; The value of simVeritimeTopLevelModuleName is hard-coded to be the
; string "vttest.vttop". This restriction will be relaxed in the 4.3 release.
;simVeritimeTopLevelModuleName      = "vttest.vttop"
         
;The -default- association of the instance of the symbol on the 
;schematic design with the corresponding simulator or schematic primitive.
;veritimeSimViewList = '( "functional" "hdl" "schematicl" "schematic" "symbol")
         
;The -default- search path list for the appropriate target 
;Veritime description of the symbol.
;veritimeSimStopList = '( "functional" "behavioral" "system" "symbol")
         
;The -default- Veritime executable in the hierarchy.
;veritimeSimBinary  = prependInstallPath("bin/veritime")
         
;A file of command line options invoked using the -f option. 
;simVeritimeInvocationOptionsFile = "<veritime/passcode_file>"
         
;Veritool path-directory of library models invoked by the -y option.
;simVeritimeLibraryDirectory = "<ASIC_or_PCB_libraries_path_dir>" 
         
;Veritool path-file of library models (usually UDP's) ;invoked by the -v option.
;simVeritimeLibraryFile = "<ASIC_or_PCB_UDP_libraries_path_file>" 
        
;Initialization options or a list of commands invoked by -i which will 
;run upon Veritime invocation.
;simVeritimeInteractiveCommandFile = "<your Veritime startup batch path-name>"
         
;Additional invocation options to be used in the Veritime invocation
;in the Veritime window. 
;simVeritimeInvocationOptions = "+libext+.v+ -p<passcode>\
;                                 +global_loops+15 +delay_mode_veritime\
;                                 +libverbose +time_scale1.000000e-09"
         
;Setting this variable to nil eliminates Path Display errors for
;schematics where there are terminals labelled differently than the
;wires they connect to. However, this slows it down significantly.
;vtiWireLabelToTermNameFlag = nil

; STL
; simDiffInputFile = "simdiff.stl"


;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; .simrc for auCdl netlister

;; Forces terminal order from auCdl simInfo - termOrder
auCdlCDFPinCntrl = 't

; List of views to open for each cell when traversing the design 
; hierarchy during netlisting and name translation
;cdlSimViewList = list("auCdl" "schematic" "cmos_sch" "cmos.sch")

; Next part solves auCdl netlister problem with pin names starting
; with a number
; - simNetNamePrefix set to "" to supress default "N" prefix
; - auCdl will also automatically re-order pins from 0. To enforce auCdl 
;   to perverse the original names it is necessary to add hnlMapNetFirstChar
;simNetNamePrefix = ""
;hnlMapNetFirstChar = list( '("0" "0") '("1" "1") '("2" "2") '("3" "3")
;  '("4" "4") '("6" "6") '("7" "7") '("8" "8") '("9" "9") )
;This section was inactivated because it caused failure of OSS netlister in AMS simulator (see ticket #040521)
