Index of /XTRAIL/WORKAREA/DIGITAL

Icon  Name                    Last modified      Size  Description
[PARENTDIR] Parent Directory                             -   
[   ] 0849386020.pdf          2018-07-19 23:49   18M  
[   ] 1118841093.pdf          2018-07-19 23:47   21M  
[   ] AMS configuration ca..> 2018-07-19 23:39  751K  
[   ] ASIC-IC_Design-for-T..> 2018-06-08 10:49  3.0M  
[   ] ATPG.docx               2018-06-05 15:03  609K  
[   ] DFT.docx                2018-07-24 18:00  768K  
[   ] DFT.pptx                2018-07-25 14:08  5.0M  
[   ] DFT02.pptx              2018-07-25 17:53  2.9M  
[   ] DFT03.pptx              2018-07-25 23:24  3.0M  
[   ] DFT04.pptx              2018-07-26 18:02  3.5M  
[   ] DFT04_tag_vacances_2..> 2018-07-27 17:09  3.5M  
[   ] DFT scan.pptx           2018-07-19 23:40  2.7M  
[   ] Defect-Oriented_Test..> 2018-06-11 12:40  5.8M  
[   ] Digital design.docx     2018-07-19 23:42  1.6M  
[   ] FSM doc.docx            2018-07-19 23:39  405K  
[   ] FSM tuto.docx           2018-07-19 23:39  693K  
[   ] Finite State Machine..> 2018-07-19 23:46  2.8M  
[   ] GSCLIB045_user_guide..> 2018-07-19 23:44  534K  
[   ] IRUN.docx               2018-07-19 23:38  275K  
[   ] Le cumul entre deux ..> 2018-07-27 14:19  555K  
[   ] Role of HDL.docx        2018-07-19 23:41  148K  
[   ] Test generation.pptx    2018-07-19 23:38  1.9M  
[   ] Timing_Analysis_Book..> 2017-09-05 15:57  3.5M  
[   ] Transparents_Int_Sys..> 2018-07-22 18:49  2.6M  
[   ] VLSI TESTING.docx       2018-07-22 18:50  1.0M  
[   ] Verilog Rise edge de..> 2018-07-19 23:38  383K  
[   ] Xilinx ISE Design Su..> 2018-07-19 23:40  681K  
[IMG] beer-2351051_1920-20..> 2023-06-28 23:23  661K  
[   ] circuit digital.docx    2018-07-19 23:40  1.0M  
[   ] digital.docx            2018-07-19 23:43  118K  
[   ] doc innovus.docx        2018-07-19 23:38   14K  
[   ] encounter.docx          2018-07-19 23:43  522K  
[   ] gpdk045_drc.pdf         2018-07-19 23:44  920K  
[   ] gpdk045_pdk_referenc..> 2018-07-19 23:44  873K  
[   ] iddq.pdf                2018-06-05 12:39  136K  
[   ] iddqmadeeasy.pdf        2018-06-05 12:37  184K  
[   ] innovus.docx            2018-07-19 23:39  633K  
[   ] innovus.pptx            2018-07-20 09:36  1.8M  
[   ] modelsim_exemples.docx  2018-07-19 23:40  1.1M  
[   ] nclaunch.docx           2018-07-19 23:42  3.0M  
[   ] questions DFT.docx      2018-07-27 17:12   13K  
[   ] scan chain.docx         2018-07-19 23:38  316K  
[   ] slides.pptx             2018-07-19 23:41   65K  
[   ] verilog_code.docx       2018-07-19 23:43  362K  
[   ] verilog annexe.pptx     2018-07-19 23:43  6.6M  
[   ] verilog complete.pptx   2018-07-19 23:41  1.5M  
[   ] verilog fork join.docx  2018-07-19 23:39  119K  
[   ] verilog global.pptx     2018-07-19 23:41  2.0M  
[   ] verilog synthesis.pptx  2018-07-19 23:41  1.2M  
[   ] work.pptx               2018-07-22 18:49  2.3M