Performed block level synthesis and place and route of major design blocks.

Designed and developed blocks from RTL to GDSII

Built full chip floor-plan including pin placement, partitions and power grid. 

Front-end RTL 

Support assistant to Digital Team:

Executed RTL design, block-level verification for various blocks and system-level verification, and silicon validation.


Digital Design Engineer Resume

Perform coding, block level verification and work with Verification team to validate the design
Run synthesis, CDC checking, equivalence checking and ATPG
Micro architect, develop specification and perform detailed logic design at the block level
Develop and execute test plans from scratch for IPs based on specification
Implement and execute power management flow

Work with Physical Implementation Team to perform synthesis, static timing analysis, place and route, etc



    Work with Physical Implementation Team to perform synthesis, static timing analysis, place and route, etc
    Follow product design flow and actively seek areas of improvement to enhance ways of working
    Support or execute product validation and debug activities working with Product, Quality and Test engineering up to production ramp-up
    Driveand/or support risk assessment, risk management and Design/Product FMEAs
    Developing digital micro architecture spec and Verilog RTL
    Drive Continuous Improvements of Products and Processes
    Performing block-level functional simulation/verification




    Perform digital design work across all aspects of the design flow from RTL to GDS
    Develop synthesis constraints and perform logic synthesis
    Perform thorough verification planning and execute firmware based verification
    Working within the chip lead and analog/power designer to implement a next-generation wireless power SOC
    Performing logic synthesis, DFT insertion, timing analysis and timing closure
    Interact with technical leaders of the company and senior staff in engineering, marketing, and corporate development to help ensure successful development of high value technologies and IP
    Taking ownership of the technical design aspects of developing an IoT compute sub-system