

module pfd (inh_NmosB, inh_PmosB, inh_gnd, inh_vdd, clk, dn, dnb, ref,
    reset, up, upb);

//port section 
   inout inh_NmosB;
   inout inh_PmosB;
   inout inh_gnd;
   inout inh_vdd;
   input clk;
   output dn;
   output dnb;
   input ref;
   input reset;
   output up;
   output upb;
   electrical ground;

//end port section 

   inv2  I9 (inh_NmosB, inh_PmosB, inh_gnd, dnb, dn, inh_vdd);
   inv2  I10 (inh_NmosB, inh_PmosB, inh_gnd, upb, up, inh_vdd);
   nor2  I27 (reset, net21, inh_NmosB, inh_PmosB, inh_gnd, net14, inh_vdd);
   nand4  I6 (net51, net44, net41, net36, inh_NmosB, inh_PmosB, inh_gnd,
    net19, inh_vdd);
   inv1  I11 (inh_NmosB, inh_PmosB, inh_gnd, net19, net21, inh_vdd);
   inv1  I24 (inh_NmosB, inh_PmosB, inh_gnd, net14, net24, inh_vdd);
   inv1  I15 (inh_NmosB, inh_PmosB, inh_gnd, net24, net40, inh_vdd);
   nand3  I7 (net40, net41, net36, inh_NmosB, inh_PmosB, inh_gnd, dnb,
    inh_vdd);
   nand3  I8 (net51, net44, net40, inh_NmosB, inh_PmosB, inh_gnd, upb,
    inh_vdd);
   nand2  I0 (upb, ref, inh_NmosB, inh_PmosB, inh_gnd, net51, inh_vdd);
   nand2  I1 (net47, net51, inh_NmosB, inh_PmosB, inh_gnd, net44, inh_vdd);
   nand2  I2 (net44, net40, inh_NmosB, inh_PmosB, inh_gnd, net47, inh_vdd);
   nand2  I3 (net41, net40, inh_NmosB, inh_PmosB, inh_gnd, net38, inh_vdd);
   nand2  I4 (net38, net36, inh_NmosB, inh_PmosB, inh_gnd, net41, inh_vdd);
   nand2  I5 (dnb, clk, inh_NmosB, inh_PmosB, inh_gnd, net36, inh_vdd);

endmodule // pfd 

