

module pll (inh_NmosB, inh_PmosB, inh_gnd, inh_vdd, net0, chpbias, net1,
    out, ref, reset, vcobias);

//port section 
   inout inh_NmosB;
   inout inh_PmosB;
   inout inh_gnd;
   inout inh_vdd;
   inout net0;
   input chpbias;
   inout net1;
   output out;
   input ref;
   input reset;
   input vcobias;
   electrical ground;

//end port section 

   vco  I0 (inh_NmosB, inh_PmosB, inh_gnd, net0, net1, vcobias, vcoOut,
    reset, filter, inh_vdd);
   pfdchp  I2 (inh_NmosB, inh_PmosB, net1, inh_gnd, inh_vdd, net0, divclk,
    chpbias, filter, ref, reset);
   dffr  I6 (net28, net23, net26, net23, ffreset, inh_NmosB, inh_PmosB,
    inh_gnd, net0);
   dffr  I7 (divIn, net28, net12, net28, ffreset, inh_NmosB, inh_PmosB,
    inh_gnd, net0);
   dffr  I3 (net23, net33, divclk, net33, ffreset, inh_NmosB, inh_PmosB,
    inh_gnd, net0);
   inv1  I5 (inh_NmosB, inh_PmosB, inh_gnd, vcoOut, divIn, net0);
   inv1  I4 (inh_NmosB, inh_PmosB, inh_gnd, vcoOut, out, net0);
   inv1  I1 (inh_NmosB, inh_PmosB, inh_gnd, reset, ffreset, net0);

//Spice primitive instantiations
      electrical net1;
   analog begin
      $spice_prim(".import vdd!");
      $spice_prim("R0  net7 filter  20k ");
      $spice_prim("C1  filter net1  5p ");
      $spice_prim("C0  net7 net1  58p ");
   end
//end Spice primitive instantiations


endmodule // pll 

