// Verilog-AMS cds_globals module for top-level cell:
//      ether_sims/top_sim.
// Generated by AMS.
// Cadence Design Systems, Inc.

`include "disciplines.vams"

module cds_globals;

// Global Signals
    wire \VDD! ;
    wire \VSS! ;
    wire \vss! ;
    wire \vdda! ;
    electrical \gnd! ;
    ground \gnd! ;

// Design Variables
    dynamicparam real fvco = 2.5E+09;
    dynamicparam real R = 100;
    dynamicparam real freq = 4.16667E+08;
    dynamicparam real vdd_1p0 = 1.0;
    dynamicparam real vdd_nom = 2.5;
    dynamicparam real freg = 4.16667E+08;

endmodule
