// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module AEQ_lvlshft_1p0_to_2p5 ( pole_2p5,gain_1p0,zero_1p0,pole_1p0,
VDD_1p0,zero_2p5,gain_2p5,VDD_2p5,VSS ); 

output [1:0]  pole_2p5;
input [4:0]  gain_1p0;
input [6:0] 
 zero_1p0;
input [1:0]  pole_1p0;
input   VDD_1p0;
output [6:0] 
 zero_2p5;
output [4:0]  gain_2p5;
input   VDD_2p5;
input   VSS;

 
 
 
level_shifter_1p0_2p5 (*
integer library_binding = "ether";
integer 
elaboration_binding = "I_gain[4:0]";
 *)
I_gain_4 ( .IN( gain_1p0[4] ), 
.VDD_1p0( VDD_1p0 ), .VDD_2p5( VDD_2p5 ), .OUT( gain_2p5[4] ), .VSS( 
VSS ) ),
  I_gain_3 ( .IN( gain_1p0[3] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( gain_2p5[3] ), .VSS( VSS ) ),
  I_gain_2 ( .IN( gain_1p0[2] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( gain_2p5[2] ), .VSS( VSS ) ),
  I_gain_1 ( .IN( gain_1p0[1] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( gain_2p5[1] ), .VSS( VSS ) ),
  I_gain_0 ( .IN( gain_1p0[0] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( gain_2p5[0] ), .VSS( VSS ) );
level_shifter_1p0_2p5 (*
integer library_binding = "ether";
integer 
elaboration_binding = "I_pole[1:0]";
 *)
I_pole_1 ( .IN( pole_1p0[1] ), 
.VDD_1p0( VDD_1p0 ), .VDD_2p5( VDD_2p5 ), .OUT( pole_2p5[1] ), .VSS( 
VSS ) ),
  I_pole_0 ( .IN( pole_1p0[0] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( pole_2p5[0] ), .VSS( VSS ) );
level_shifter_1p0_2p5 (*
integer library_binding = "ether";
integer 
elaboration_binding = "I_zero[6:0]";
 *)
I_zero_6 ( .IN( zero_1p0[6] ), 
.VDD_1p0( VDD_1p0 ), .VDD_2p5( VDD_2p5 ), .OUT( zero_2p5[6] ), .VSS( 
VSS ) ),
  I_zero_5 ( .IN( zero_1p0[5] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( zero_2p5[5] ), .VSS( VSS ) ),
  I_zero_4 ( .IN( zero_1p0[4] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( zero_2p5[4] ), .VSS( VSS ) ),
  I_zero_3 ( .IN( zero_1p0[3] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( zero_2p5[3] ), .VSS( VSS ) ),
  I_zero_2 ( .IN( zero_1p0[2] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( zero_2p5[2] ), .VSS( VSS ) ),
  I_zero_1 ( .IN( zero_1p0[1] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( zero_2p5[1] ), .VSS( VSS ) ),
  I_zero_0 ( .IN( zero_1p0[0] ), .VDD_1p0( VDD_1p0 ), .VDD_2p5( 
VDD_2p5 ), .OUT( zero_2p5[0] ), .VSS( VSS ) );

endmodule
