// Verilog-AMS netlist generated by the AMS netlister, version 5.10.41_USR1.7.37.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module pll_250MHz_ams_sim ( phase ); 

output [10:0]  phase;

 
 
 
PLL_250MHZ (*
integer library_binding = "ether";
 *)
I29 ( .CLK_250MHZ_PH( 
phase[10:0] ), .SIDDQ( cds_globals.\gnd!  ), .IPLY_25u( net025 ), .DISABLE( 
cds_globals.\gnd!  ), .IEXT_100u( net022 ), .CLK_25MHZ( net011 ), .CP_ITEST_25u( 
net11 ), .VDD( VDD ), .IEXT_25u( net024 ), .VSS( cds_globals.\gnd!  ) );
 
clock_monitor2 (*
integer library_binding = "ether_sims";
 *)
I64 ( .jitter_e2e( 
jVCO_CLK ), .clockref( phase[0] ), .clockref_bar( cds_globals.\gnd!  ), 
.duty( dcVCO_CLK ), .freq( fVCO_CLK ), .threshvoltm( 
cds_globals.\gnd!  ), .threshvoltp( VTHRESH ) );
 
resistor #(.r(10K)) (*
integer library_binding = "analogLib";
 *)
R2
 ( VTHRESH, cds_globals.\gnd!  );
resistor #(.r(10K)) (*
integer library_binding = "analogLib";
 *)
R1
 ( VDD, VTHRESH );
resistor #(.r(40K)) (*
integer library_binding = "analogLib";
 *)
R6
 ( net030, cds_globals.\gnd!  );
 
vsource #(.type("pulse"), .period(40n), .width(19.8n), .val0(0.0), .rise(200p),
 .val1(2.5 * cds_globals.VMULT), .fall(200p)) (*
integer 
library_binding = "analogLib";
 *)
V1 ( net011, cds_globals.\gnd!  );
 
isource #(.type("dc"), .dc(25u)) (*
integer library_binding
 = "analogLib";
 *)
I1 ( net024, cds_globals.\gnd!  );
isource #(.type("dc"), .dc(100u)) (*
integer library_binding
 = "analogLib";
 *)
I3 ( net022, cds_globals.\gnd!  );
 
cccs #(.gain(-1), .probe("V0")) (*
integer library_binding
 = "analogLib";
 *)
F0 ( net025, cds_globals.\gnd!  );
 
vsource #(.type("dc"), .dc(2.5 * cds_globals.VMULT)) (*
integer 
library_binding = "analogLib";
 *)
V2 ( VDD, cds_globals.\gnd!  );
vsource #(.type("dc"), .dc(1.0)) (*
integer library_binding
 = "analogLib";
 *)
V0 ( net030, cds_globals.\gnd!  );

endmodule
