
; Sample runset for 90 nm
; technology
; DIVA(r) version 5.0 Antenna rule file
; generated by GTE Version: 03.03-a  Build: 200511302105 (7729) on Dec 1, 2005

; parameter file: 

; RELEASE NOTES FOR THE 90nm GPDK
; --------------------------------------------------------------------------------
; VERSION v2.8
; --------------------------------------------------------------------------------
; Changes:
; - Added DFM to MOS pcells and DRC rules
; - Corrected snap to grid issue with mimcap callback calculations
; - Modified the Nhvt and Phvt rules to allow integrated body ties
; --------------------------------------------------------------------------------
; VERSION v2.7
; --------------------------------------------------------------------------------
; Changes:
; - Recompiled rcx capgen files using Assura version 3.1.4 USR2
; - Added a simple mim capacitor to the PDK
; - Updated the block ICC rules
; - Returned table spacing rules to their original high to low order
; - Updated VLM rules to match AMS Flow Kit data
; - Updated Neocell rules to match AMS Flow Kit data
; - Updated Neocircuit rules to match AMS Flow Kit data
; --------------------------------------------------------------------------------
; VERSION v2.6
; --------------------------------------------------------------------------------
; Changes:
; - Updated table spacing rules to go from low to high instead of the other way
; - Renamed masco directory to pvs
; --------------------------------------------------------------------------------
; VERSION v2.5
; --------------------------------------------------------------------------------
; Changes:
; - Changed resistor schematic pcell code to support AMS in the OA22 library
; - Translated a new OA22 library using the 5.2.51 (270) build
; --------------------------------------------------------------------------------
; VERSION v2.4
; --------------------------------------------------------------------------------
; Changes:
; - Added a gds map file for SOC encounter (PCR 811195)
; - Added SOC encounter cap table files to PDK
; - Removed invalid minEnclosure rules from techfile (PCR 811741)
; - Updated layerFunctions in the techfile
; - Updated maximum via stack rules (PCR 811179)
; - Replaced fire and ice techfile with updated version (PCR 811187)
; - Added LVSInclude file to the default assura techRuleSets file (PCR 811182)
; - Reordered assura grid checks to avoid symbolic pin error (PCR 811180)
; - Removed the gpdk090 LEF file from the tar kit. Use the one located in the CDK
; - Translated a new OA22 library using the 5.2.51 (262) build
; --------------------------------------------------------------------------------
; VERSION v2.3
; --------------------------------------------------------------------------------
; Changes:
; - Corrected values in the cdb table spacing rules for wide metal
; - Changed the minimum area rules for Metal2 thru Metal7 from .09 to .08
; - Renamed all references of *.cdba to *.cdb
; --------------------------------------------------------------------------------
; VERSION v2.2
; --------------------------------------------------------------------------------
; Changes:
; - Added "gec3DBUPerUU" property to cdb library for SOCE
; - Removed LEF information from DFII techfiles shipped with PDK
; - Layer Function order in techfiles was updated
; - Translated a new OA22 library using the 5.2.51 (212) build
; --------------------------------------------------------------------------------
; VERSION v2.1
; --------------------------------------------------------------------------------
; Changes:
; - Converted a new OA22 library using the 5.2.51 (194) build
; - Updated Reference Manual to match latest revisions
; - Changed viaRule definition in the techfile to avoid an issue in OA2.2
; - Changed via definition in the LEF file to avoid an issue in OA2.2
; - Changed layer routing direction error in the techfile
; - Updated Diva, Assura, and Masco PV rules for pin layer issue
; - Updated the hilite definitions is the display.drf file
; --------------------------------------------------------------------------------
; VERSION v2.0
; --------------------------------------------------------------------------------
; Changes:
; - Changed Thick Oxide to Oxide spacing to 0.28um (PCR 769709)
; - Converted a new OA22 library using the 5.2.51_Beta1 (170) build
; - Changed the mos simulation values for hv_u0_ne and hv_u0_pe (PCR 782125)
; - Added initial release of the Masco DRC rules
; - Corrected inconsistency with vertical pnp LVS netlisting (PCR773581)
; --------------------------------------------------------------------------------
; VERSION v1.1.2
; --------------------------------------------------------------------------------
; Changes:
; - Added OA22 version of the gpdk090 library to the hierarchy
; - Added missing display.drf files to OA libraries
; --------------------------------------------------------------------------------
; VERSION v1.1.1
; --------------------------------------------------------------------------------
; Changes:
; - Added library name to Diva and Assura extract decks
; - Changed auCdl names to match auLvs names
; - Updated MergePinAndNet switch in verification rules (PCR 765134)
; - Added net purpoese to stream map for Metal1-9 layers 
; - Changed Bondpad width from 55um to 52um
; - Updated and included ascii techfiles for cdb and oa2.0 to include icc.rules
; - Added icc.block.rules for vcr routing at the top level
; - Included reliability analysis mos scs model file for spectre
; - Updated LVSinclude.rsf file to include bus binding
; - Updated technology lef file and read the new lef into the OA2.0 techfile
; - Added Row Boundary lpp to the valid layer list but turned display off
; - Added library name to extraction statements for Diva and Assura (PCR 661962)
; - Excluded bond pads from slot DRC checks
; - Updated rule NWR.O.1 for the nwell resistor
; --------------------------------------------------------------------------------
; VERSION v1.1.0
; --------------------------------------------------------------------------------
; Changes:
; - Updated Nwell to Nburied spacing rules to allow for isolated guardrings
; - Fixed AMS error in diode CDF's
; - Updated callback checks for vpnp's and diodes
; - Updated via stacking rules to fix false errors in standard cell library
; - Added MergePinAndNet switch to assura rules
; - Fixed DRC spacing errors in resistor guardrings
; - Removed butting body tie option for Native Nmos devices
; - Changed OXIDE.SP.3 from 0.18um to 0.15um
; --------------------------------------------------------------------------------
; VERSION v1.0.9
; --------------------------------------------------------------------------------
; Changes:
; - Changed location of the cds.lib, assura_tech.lib, and VERSION files(PCR 739543)
; - Moved the location of the SNA files to reduce the hierarchy (PCR 739543)
; - Added "RowBnd" to the display.drf
; - Changed minimum bond pad width from 55um to 52um
; - Added Oxide-thk to the avextracted view created by Assura (PCR 723424)
; - Added geomCat to extract deck for RCX issue (PCR 757885)
; - Added stretchable bipolar npn and pnp devices to the PDK (PCR 753173)
; - Added PAS generated NEOCELL files to the PDK
; - Removed old voltageStorm data and linked to appropriate FireIce file
; --------------------------------------------------------------------------------
; VERSION v1.0.8
; --------------------------------------------------------------------------------
; Changes:
; - Fixed problem in VXL with Moscap Abuttment (PCR 749878)
; - Added extra enclosure rules in the techfile for Qcells (PCR 703810)
; - Added extra net layers to Assura extract for Oxide and Nwell (PCR 723424)
; - Updated icc.rules file to allow wire editor routing (PCR 709239)
; - Updated compare rules to allow for iterated dummy resistors (PCR 745597)
; - Updated compare rules to fix problem with moscap "m" factors (PCR 752307)
; - Added Assura LVS support for isolated mos devices (PCR 738123)
; - Fixed false DRC errors related to LATCHUP.3 rule
; - LEF technology file is compiled into the DFII binary for OA2.0 (PCR 749574)
; - Added Voltage Storm data file to pdk hierarchy (PCR 718488)
; --------------------------------------------------------------------------------
; VERSION v1.0.7
; --------------------------------------------------------------------------------
; Changes:
; - Updated Assura and Diva LVS rules for series and parallel resistor(PCR 742782)
; - Added MOS capacitor entry modes for the MOS capacitors (PCR 742414)
; - Added missing net purposes for Assura extracted view (PCR 723424)
; - Added missing display.drf references in the OA2.0 techfile
; --------------------------------------------------------------------------------
; VERSION v1.0.6
; --------------------------------------------------------------------------------
; Changes:
; - Updated Assura and Diva LVS support for vpnp2, vpnp5, vpnp10 (PCRs 722588, 721948) 
; - Updated icc.rules file (PCR 726635)
; - Added LVSinclude.rsf file to Assura (PCR 737155)
; - Updated prRules to add contact definition for Abstract tool (PCR 739914)
; - Added VLM support in directory "vlm" (PCR 718487)
; - Added VAVO support in directory "vavo"
; --------------------------------------------------------------------------------
; VERSION v1.0.5
; --------------------------------------------------------------------------------
; Changes:
; - Remove Bondpad metals from MSLOT1_W_1_MSLOT2_L_1 (M1-M9).
; - Changed bondpad_metalx and appended andnot metalx_slot.
; - Changed bondpad_sq def. to size down/up rather than >.
; - Added missing metal and via in bondpad checks.
; - Rewrote BONDPAD_L_1
; - Corrected definition of bomdpad_metalx_filled
; - Removed bondpad metals from METALx_SLOT.E.1 checks
; - Split BONDPAD_B1 into two macros.
; - Reworded comments at top of Bondpad DRC.
; - Updated MOSCAP symbols per PCR 721436
; - Added ams simInfo/view to res.
; --------------------------------------------------------------------------------
; VERSION v1.0.4
; --------------------------------------------------------------------------------
; Changes:
; - ESD.14 rule was changed from 0.4 to 0.3 
; - ESD.4 for p-type corrected
; --------------------------------------------------------------------------------
; VERSION v1.0.3
; --------------------------------------------------------------------------------
; Changes:
; - Changed device extraction to extract 'fw' (finger width) and 'simW' for mos devices in addition to w & l.
; - Changed device extraction to extract segL, segW and segR for resistors in addition to w & l.
; --------------------------------------------------------------------------------
; VERSION v1.0.2
; --------------------------------------------------------------------------------
; Changes:
; - Merge metal drawing and pin purposes
; --------------------------------------------------------------------------------
; VERSION v1.0.1
; --------------------------------------------------------------------------------
; Changes:
; - Updated existing Bondpad rules and added additional rules
; - Added missing design rules to DFII techfile (PCR#703810)
; - Updated icc.rules file (PCR#703789)
; - Updated 'minSpacing Nimp to Pimp' in DFII techfile from 18.0 to 0.18
; - Fixed resistor callback problem when switching instance masters
; - Fixed cdsVias in DFII techfile
;  
; --------------------------------------------------------------------------------
; VERSION v1.0.0
; --------------------------------------------------------------------------------
; New:
; - Pin purpose support for LVS
; - Subcircuit model for nmos1v_iso
; - Added Fire & Ice technology file and layermaps
; - Added SNA technology files
; - Added PDK reference manual
; - Added LPPs required by NeoCell to DFII techfile
; Changes:
; - Updated Resistor Pcell for PAS 2.8
; - Updated MOS devices: added QCell abutment compatibility, added
;  abutClass device property, added upper limits for m, tapCntRows,
;  and fingers. Updated implant enclosure for compatibility with QCells.
; - Updated dielectric table add Pass1 & Pass2
; - Change default value for region to " " (MOSFETs)
; --------------------------------------------------------------------------------
; VERSION v0.5.7
; --------------------------------------------------------------------------------
; New:
; - Added 3-term moscap device
; - Added SNA layer and layer purposes required by SNA tool
; Changes:
; - Removed gpdk090_tech_9lm-lite.lef file and resulting vias from GPDK
; - Included latest gpdk090_tech_9lm.lef (v 0.6) 
; - Re-ran LEFIN with latest lef file.
; - Fixed generated techfile sections.
; - Fixed metal9 layer function.
; - Change Assura decks to include 'pin' purpose
; --------------------------------------------------------------------------------
; VERSION v0.5.6
; --------------------------------------------------------------------------------
; Changes:
; - Added prBoundary to stream file
; - Fixed resistor netlist problem
; - Added material to layerRules for CCAR
; --------------------------------------------------------------------------------
; VERSION v0.5.5
; --------------------------------------------------------------------------------
; New: 
; - Added gpdk090_tech_9lm-lite.lef file from M. Linnik to work around via issues.
; Changes:
; - Added missing layer purposes to cdb version of techfile.
; - Ran lef-in with gpdk090_tech_9lm-lite.lef file
; --------------------------------------------------------------------------------
; VERSION v0.5.4
; --------------------------------------------------------------------------------
; New:
; - Added vpnps (2x2,5x5,10x10)
; - Added metal resistors
; - Added LEF technology file
; - Added SOC Encounter cap tables
; Changes:
; - Changed METALk.SP.1.1 (k=8,9) from 0.44u to 0.40um.
; - Changed parallel run length for METALk.SP.1.2 (k=1..7) from 0.50u to 0.56u (spacing stayed the same)
; - Fixed error message for VIAk.X.1 and VIAk.X2 (k=1..6)
; - Added missing ivpcell view for resistors
; - Added layer stream map table
; - Removed rule POLYR.X.2 (Poly resistors must have Salicide Block)
; - Fixed contact poly spacing violation in salicided poly resistors
; - Added post lef-in sections to DFII techfile
; --------------------------------------------------------------------------------
; VERSION v0.5.3
; --------------------------------------------------------------------------------
; Changes:
; - Added recognition layer to moscaps
; - Added moscaps to LVS
; - Updated LVS for nmos/pmos 1.2/2.5
; --------------------------------------------------------------------------------
; VERSION v0.5.2
; --------------------------------------------------------------------------------
; New: 
; - Added 2v moscaps.
; Changes:
; - Fixed LVS to recognize poly resistors on nwell.
; - Fix problem with wrong model references.
; - Fixed resistor pcells. Removed recognition layer from dummy resistors
; --------------------------------------------------------------------------------
; VERSION v0.5.1
; --------------------------------------------------------------------------------
; Changes:
; - Moved dbu/uu setting in .cdsenv to top of file because of Assura issue.
; --------------------------------------------------------------------------------
; VERSION v0.5.0
; --------------------------------------------------------------------------------
; New:
; - Added initial version of moscaps
; - Added extract & compare rules for resistors, diode and moscaps.
; - Updated the device model names on mos device CDFs to match model files.
; - Added revison history to rule decks
; Changes:
; - Replaced icc.rules file with version from OBAX
; - Removed METALk.EA.1 (k=1..9) rules
; - Removed METALk.SP.3 (k=1..9) rules
; --------------------------------------------------------------------------------
; VERSION v0.4.2
; --------------------------------------------------------------------------------
; Changes:
; - Fixed false error in rule METAL1.SP.3
; - Fixed false error in METLAk.SP.3 (k=2..7) 
; - Changed VIAk.SP.1 from 0.18u to 0.15u to allow smaller routing grid
;  
; --------------------------------------------------------------------------------
; VERSION v0.4.1
; --------------------------------------------------------------------------------
; New:
; - Added 90nm spectre models for MOS devices
; Changes:
; - Updated the gpdk090_DRM.pdf file under docs directory.
; - Changed VIAk.E.1 from 0.02 to 0.005
; - Changed METALk.E.1 from 0.03 to 0.005
; - Changed METALk.E.2 from 0.08 to 0.06
; - Changed Tox for MOS devices
; - Changed layout grid spacing from 0.01 to 0.005 to match mfg grid
; --------------------------------------------------------------------------------
; VERSION v0.4.0
; --------------------------------------------------------------------------------
; New:
; - Added Resistor and diodes (Pcells, Symbols, CDF and SimViews)
; - Added Bondpad rules to DRC
; - Added icc.rules file to techFiles directory
; Changes:
; - Changed max gate width and lenght to 30u for mos devices
; - Fixed inconsistent dbu/uu on symbolics
; --------------------------------------------------------------------------------
; VERSION v0.3.2 
; --------------------------------------------------------------------------------
; New:
; - Added Ntap (M1_NWELL) and Ptab (M1_PSUB) symbolic contacts 
;   (can not implement them with cdsViaDevices since they only support 3 layers)
; Changes/Fixes:
; - Changed POLY.SP.2 and POLY.SP.3 from 0.2u to 0.12u (per Shufans request)
; - Changed NIMP.SE.3 and PIMP.SE.3 from 0.28um to 0.18u (per Shufans request)
; - Fixed problem with nmos/pmos devices SD/Gate connection in VXL
; - Fixed M2_M1 cdsViaDevice Metal1-Via1 Enclosure
; --------------------------------------------------------------------------------
; VERSION v0.3.1 
; --------------------------------------------------------------------------------
; New:
; - prRules section
; - ccar rules section
; - cdsViaDevices
; - multiPartPath 
; Changes:
; - Changed stipple patterns for Nimp and Pimp
; - Added prefix to model names in CDF and model files
; - Removed metal spacing rule for w <= 0.18 and l <=0.5
; - Changed CONT.E.4 from 0.08 to 0.06.
; - Changed METAL1.E.1 from 0.02 to 0.00.
; - Changed NIMP.E.2 from 0.04 to 0.02.
; - Changed PIMP.E.2 from 0.04 to 0.02.
; - Changed NIMP.SE.2 from 0.04 to 0.02.
; - Changed PIMP.SE.2 from 0.04 to 0.02.
; - Changed OXIDE.SP.3 fro 0.20 to 0.18.
; --------------------------------------------------------------------------------
; VERSION v0.3.0 
; --------------------------------------------------------------------------------
; New:
; - Added prelim. device models to PDK
; - Initial PDK release with MOS devices (CDF, callbacks, PCells, SimViews) OA2.0 and CDB
; - Added Psub layer
; Bug fixes
; - Removed Pwell from Assura Extract file
; --------------------------------------------------------------------------------
; VERSION v0.2.0 
; --------------------------------------------------------------------------------
; New:
; - Initial Assura LVS/RCX
; --------------------------------------------------------------------------------
; VERSION v0.1.0 (initial version)
; --------------------------------------------------------------------------------
; New:
; - Basic Assura DRC (no pad and esd rules)
; Bug fixes:
; -
; DRC and LVS and TECHFILE 
; RELEASE NOTES FOR THE 90nm GPDK
; --------------------------------------------------------------------------------
; VERSION v0.5.2
; --------------------------------------------------------------------------------
; New: 
; - Added 2v moscaps.
; Changes:
; - Fixed LVS to recognize poly resistors on nwell.
; - Fix problem with wrong model references.
; - Fixed resistor pcell problem. Removed recognition layer from dummy resistors.
; --------------------------------------------------------------------------------
; VERSION v0.5.1
; --------------------------------------------------------------------------------
; Changes:
; - Moved dbu/uu setting in .cdsenv to top of file because of Assura issue.
; --------------------------------------------------------------------------------
; VERSION v0.5.0
; --------------------------------------------------------------------------------
; New:
; - Added initial version of moscaps
; - Added extract & compare rules for resistors, diode and moscaps.
; - Updated the device model names on mos device CDFs to match model files.
; - Added revison history to rule decks
; Changes:
; - Replaced icc.rules file with version from OBAX
; - Removed METALk.EA.1 (k=1..9) rules
; - Removed METALk.SP.3 (k=1..9) rules
; --------------------------------------------------------------------------------
; VERSION v0.4.2
; --------------------------------------------------------------------------------
; Changes:
; - Fixed false error in rule METAL1.SP.3
; - Fixed false error in METLAk.SP.3 (k=2..7) 
; - Changed VIAk.SP.1 from 0.18u to 0.15u to allow smaller routing grid
;  
; --------------------------------------------------------------------------------
; VERSION v0.4.1
; --------------------------------------------------------------------------------
; New:
; - Added 90nm spectre models for MOS devices
; Changes:
; - Updated the gpdk090_DRM.pdf file under docs directory.
; - Changed VIAk.E.1 from 0.02 to 0.005
; - Changed METALk.E.1 from 0.03 to 0.005
; - Changed METALk.E.2 from 0.08 to 0.06
; - Changed Tox for MOS devices
; - Changed layout grid spacing from 0.01 to 0.005 to match mfg grid
; --------------------------------------------------------------------------------
; VERSION v0.4.0
; --------------------------------------------------------------------------------
; New:
; - Added Resistor and diodes (Pcells, Symbols, CDF and SimViews)
; - Added Bondpad rules to DRC
; - Added icc.rules file to techFiles directory
; Changes:
; - Changed max gate width and lenght to 30u for mos devices
; - Fixed inconsistent dbu/uu on symbolics
; --------------------------------------------------------------------------------
; VERSION v0.3.2 
; --------------------------------------------------------------------------------
; New:
; - Added Ntap (M1_NWELL) and Ptab (M1_PSUB) symbolic contacts 
;   (can not implement them with cdsViaDevices since they only support 3 layers)
; Changes/Fixes:
; - Changed POLY.SP.2 and POLY.SP.3 from 0.2u to 0.12u (per Shufans request)
; - Changed NIMP.SE.3 and PIMP.SE.3 from 0.28um to 0.18u (per Shufans request)
; - Fixed problem with nmos/pmos devices SD/Gate connection in VXL
; - Fixed M2_M1 cdsViaDevice Metal1-Via1 Enclosure
; --------------------------------------------------------------------------------
; VERSION v0.3.1 
; --------------------------------------------------------------------------------
; New:
; - prRules section
; - ccar rules section
; - cdsViaDevices
; - multiPartPath 
; Changes:
; - Changed stipple patterns for Nimp and Pimp
; - Added prefix to model names in CDF and model files
; - Removed metal spacing rule for w <= 0.18 and l <=0.5
; - Changed CONT.E.4 from 0.08 to 0.06.
; - Changed METAL1.E.1 from 0.02 to 0.00.
; - Changed NIMP.E.2 from 0.04 to 0.02.
; - Changed PIMP.E.2 from 0.04 to 0.02.
; - Changed NIMP.SE.2 from 0.04 to 0.02.
; - Changed PIMP.SE.2 from 0.04 to 0.02.
; - Changed OXIDE.SP.3 fro 0.20 to 0.18.
; --------------------------------------------------------------------------------
; VERSION v0.3.0 
; --------------------------------------------------------------------------------
; New:
; - Added prelim. device models to PDK
; - Initial PDK release with MOS devices (CDF, callbacks, PCells, SimViews) OA2.0 and CDB
; - Added Psub layer
; Bug fixes
; - Removed Pwell from Assura Extract file
; --------------------------------------------------------------------------------
; VERSION v0.2.0 
; --------------------------------------------------------------------------------
; New:
; - Initial Assura LVS/RCX
; --------------------------------------------------------------------------------
; VERSION v0.1.0 (initial version)
; --------------------------------------------------------------------------------
; New:
; - Basic Assura DRC (no pad and esd rules)
; Bug fixes:
; -
; DRC and LVS and TECHFILE 
; RELEASE NOTES FOR THE 90nm GPDK
; --------------------------------------------------------------------------------
; VERSION v0.5.2
; --------------------------------------------------------------------------------
; New: 
; - Added 2v moscaps.
; Changes:
; - Fixed LVS to recognize poly resistors on nwell.
; - Fix problem with wrong model references.
; - Fixed resistor pcell problem. Removed recognition layer from dummy resistors.
; --------------------------------------------------------------------------------
; VERSION v0.5.1
; --------------------------------------------------------------------------------
; Changes:
; - Moved dbu/uu setting in .cdsenv to top of file because of Assura issue.
; --------------------------------------------------------------------------------
; VERSION v0.5.0
; --------------------------------------------------------------------------------
; New:
; - Added initial version of moscaps
; - Added extract & compare rules for resistors, diode and moscaps.
; - Updated the device model names on mos device CDFs to match model files.
; - Added revison history to rule decks
; Changes:
; - Replaced icc.rules file with version from OBAX
; - Removed METALk.EA.1 (k=1..9) rules
; - Removed METALk.SP.3 (k=1..9) rules
; --------------------------------------------------------------------------------
; VERSION v0.4.2
; --------------------------------------------------------------------------------
; Changes:
; - Fixed false error in rule METAL1.SP.3
; - Fixed false error in METLAk.SP.3 (k=2..7) 
; - Changed VIAk.SP.1 from 0.18u to 0.15u to allow smaller routing grid
;  
; --------------------------------------------------------------------------------
; VERSION v0.4.1
; --------------------------------------------------------------------------------
; New:
; - Added 90nm spectre models for MOS devices
; Changes:
; - Updated the gpdk090_DRM.pdf file under docs directory.
; - Changed VIAk.E.1 from 0.02 to 0.005
; - Changed METALk.E.1 from 0.03 to 0.005
; - Changed METALk.E.2 from 0.08 to 0.06
; - Changed Tox for MOS devices
; - Changed layout grid spacing from 0.01 to 0.005 to match mfg grid
; --------------------------------------------------------------------------------
; VERSION v0.4.0
; --------------------------------------------------------------------------------
; New:
; - Added Resistor and diodes (Pcells, Symbols, CDF and SimViews)
; - Added Bondpad rules to DRC
; - Added icc.rules file to techFiles directory
; Changes:
; - Changed max gate width and lenght to 30u for mos devices
; - Fixed inconsistent dbu/uu on symbolics
; --------------------------------------------------------------------------------
; VERSION v0.3.2 
; --------------------------------------------------------------------------------
; New:
; - Added Ntap (M1_NWELL) and Ptab (M1_PSUB) symbolic contacts 
;   (can not implement them with cdsViaDevices since they only support 3 layers)
; Changes/Fixes:
; - Changed POLY.SP.2 and POLY.SP.3 from 0.2u to 0.12u (per Shufans request)
; - Changed NIMP.SE.3 and PIMP.SE.3 from 0.28um to 0.18u (per Shufans request)
; - Fixed problem with nmos/pmos devices SD/Gate connection in VXL
; - Fixed M2_M1 cdsViaDevice Metal1-Via1 Enclosure
; --------------------------------------------------------------------------------
; VERSION v0.3.1 
; --------------------------------------------------------------------------------
; New:
; - prRules section
; - ccar rules section
; - cdsViaDevices
; - multiPartPath 
; Changes:
; - Changed stipple patterns for Nimp and Pimp
; - Added prefix to model names in CDF and model files
; - Removed metal spacing rule for w <= 0.18 and l <=0.5
; - Changed CONT.E.4 from 0.08 to 0.06.
; - Changed METAL1.E.1 from 0.02 to 0.00.
; - Changed NIMP.E.2 from 0.04 to 0.02.
; - Changed PIMP.E.2 from 0.04 to 0.02.
; - Changed NIMP.SE.2 from 0.04 to 0.02.
; - Changed PIMP.SE.2 from 0.04 to 0.02.
; - Changed OXIDE.SP.3 fro 0.20 to 0.18.
; --------------------------------------------------------------------------------
; VERSION v0.3.0 
; --------------------------------------------------------------------------------
; New:
; - Added prelim. device models to PDK
; - Initial PDK release with MOS devices (CDF, callbacks, PCells, SimViews) OA2.0 and CDB
; - Added Psub layer
; Bug fixes
; - Removed Pwell from Assura Extract file
; --------------------------------------------------------------------------------
; VERSION v0.2.0 
; --------------------------------------------------------------------------------
; New:
; - Initial Assura LVS/RCX
; --------------------------------------------------------------------------------
; VERSION v0.1.0 (initial version)
; --------------------------------------------------------------------------------
; New:
; - Basic Assura DRC (no pad and esd rules)
; Bug fixes:
; -

drcExtractRules(
geomErase("marker" "warning")
geomErase("marker" "error")

; procedure for switches CHECK_CONT_ANT_3
procedure( switchProc0()
    geomConnect(
        via(cont_poly cont_antenna Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError0 var1 && (area(cont_antenna)/if(var1 var1 1))>15.0
            cont_antenna)
    )
    saveDerived(antError0
        "ANT.3: Poly Contact area to gate area ratio must be <= 15.0")

)

; procedure for switches CHECK_METAL1_ANT_4
procedure( switchProc1()
    geomConnect(
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError1 var1 && (area(metal1_wo_diode)/if(var1 var1 1))>475.0
            metal1_wo_diode)
    )
    saveDerived(antError1
        "ANT.4.M1: Metal1 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL1_ANT_7
procedure( switchProc2()
    geomConnect(
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError2 var1 && ((area(metal1_with_diode)/if(var1 var1
            1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal1_with_diode)
    )
    saveDerived(antError2
        "ANT.7.M1_1: Metal1 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL2_ANT_4
procedure( switchProc3()
    geomConnect(
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError3 var1 && (area(metal2_conn)/if(var1 var1 1))>475.0
            metal2_conn)
    )
    saveDerived(antError3
        "ANT.4.M2: Metal2 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL2_ANT_7
procedure( switchProc4()
    geomConnect(
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError4 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn))/if(var1 var1
            1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal2_conn)
    )
    saveDerived(antError4
        "ANT.7.M1_2: Cumulative Metal1 through Metal2 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL3_ANT_4
procedure( switchProc5()
    geomConnect(
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError5 var1 && (area(metal3_conn)/if(var1 var1 1))>475.0
            metal3_conn)
    )
    saveDerived(antError5
        "ANT.4.M3: Metal3 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL3_ANT_6
procedure( switchProc6()
    geomConnect(
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError6 var1 &&
            ((area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal3_conn)
    )
    saveDerived(antError6
        "ANT.6.M1_3: Cumulative Metal1 through Metal3 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL3_ANT_7
procedure( switchProc7()
    geomConnect(
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError7 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn)+area(metal3_conn))/if(var1
            var1 1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal3_conn)
    )
    saveDerived(antError7
        "ANT.7.M1_3: Cumulative Metal1 through Metal3 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL4_ANT_4
procedure( switchProc8()
    geomConnect(
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError8 var1 && (area(metal4_conn)/if(var1 var1 1))>475.0
            metal4_conn)
    )
    saveDerived(antError8
        "ANT.4.M4: Metal4 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL4_ANT_6
procedure( switchProc9()
    geomConnect(
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError9 var1 &&
            ((area(metal4_conn)+area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal4_conn)
    )
    saveDerived(antError9
        "ANT.6.M1_4: Cumulative Metal1 through Metal4 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL4_ANT_7
procedure( switchProc10()
    geomConnect(
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError10 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn)+area(metal3_conn)+area(metal4_conn))/if(var1
            var1 1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal4_conn)
    )
    saveDerived(antError10
        "ANT.7.M1_4: Cumulative Metal1 through Metal4 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL5_ANT_4
procedure( switchProc11()
    geomConnect(
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError11 var1 && (area(metal5_conn)/if(var1 var1 1))>475.0
            metal5_conn)
    )
    saveDerived(antError11
        "ANT.4.M5: Metal5 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL5_ANT_6
procedure( switchProc12()
    geomConnect(
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError12 var1 &&
            ((area(metal5_conn)+area(metal4_conn)+area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal5_conn)
    )
    saveDerived(antError12
        "ANT.6.M1_5: Cumulative Metal1 through Metal5 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL5_ANT_7
procedure( switchProc13()
    geomConnect(
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError13 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn)+area(metal3_conn)+area(metal4_conn)+area(metal5_conn))/if(var1
            var1 1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal5_conn)
    )
    saveDerived(antError13
        "ANT.7.M1_5: Cumulative Metal1 through Metal5 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL6_ANT_4
procedure( switchProc14()
    geomConnect(
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError14 var1 && (area(metal6_conn)/if(var1 var1 1))>475.0
            metal6_conn)
    )
    saveDerived(antError14
        "ANT.4.M6: Metal6 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL6_ANT_6
procedure( switchProc15()
    geomConnect(
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError15 var1 &&
            ((area(metal6_conn)+area(metal5_conn)+area(metal4_conn)+area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal6_conn)
    )
    saveDerived(antError15
        "ANT.6.M1_6: Cumulative Metal1 through Metal6 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL6_ANT_7
procedure( switchProc16()
    geomConnect(
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError16 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn)+area(metal3_conn)+area(metal4_conn)+area(metal5_conn)+area(metal6_conn))/if(var1
            var1 1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal6_conn)
    )
    saveDerived(antError16
        "ANT.7.M1_6: Cumulative Metal1 through Metal6 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL7_ANT_4
procedure( switchProc17()
    geomConnect(
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError17 var1 && (area(metal7_conn)/if(var1 var1 1))>475.0
            metal7_conn)
    )
    saveDerived(antError17
        "ANT.4.M7: Metal7 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL7_ANT_6
procedure( switchProc18()
    geomConnect(
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError18 var1 &&
            ((area(metal7_conn)+area(metal6_conn)+area(metal5_conn)+area(metal4_conn)+area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal7_conn)
    )
    saveDerived(antError18
        "ANT.6.M1_7: Cumulative Metal1 through Metal7 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL7_ANT_7
procedure( switchProc19()
    geomConnect(
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError19 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn)+area(metal3_conn)+area(metal4_conn)+area(metal5_conn)+area(metal6_conn)+area(metal7_conn))/if(var1
            var1 1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal7_conn)
    )
    saveDerived(antError19
        "ANT.7.M1_7: Cumulative Metal1 through Metal7 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL8_ANT_4
procedure( switchProc20()
    geomConnect(
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError20 var1 && (area(metal8_conn)/if(var1 var1 1))>475.0
            metal8_conn)
    )
    saveDerived(antError20
        "ANT.4.M8: Metal8 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL8_ANT_6
procedure( switchProc21()
    geomConnect(
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError21 var1 &&
            ((area(metal8_conn)+area(metal7_conn)+area(metal6_conn)+area(metal5_conn)+area(metal4_conn)+area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal8_conn)
    )
    saveDerived(antError21
        "ANT.6.M1_8: Cumulative Metal1 through Metal8 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL8_ANT_7
procedure( switchProc22()
    geomConnect(
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError22 var1 &&
            (((area(metal1_with_diode)+area(metal2_conn)+area(metal3_conn)+area(metal4_conn)+area(metal5_conn)+area(metal6_conn)+area(metal7_conn)+area(metal8_conn))/if(var1
            var1 1))-((area(diff_diode)*500.0)+45000.0))>0.0 metal8_conn)
    )
    saveDerived(antError22
        "ANT.7.M1_8: Cumulative Metal1 through Metal8 area to gate area ratio must be <= 45000 + (diode area * 500)")

)

; procedure for switches CHECK_METAL9_ANT_4
procedure( switchProc23()
    geomConnect(
        via(Via8 metal9_conn metal8_conn)
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError23 var1 && (area(metal9_conn)/if(var1 var1 1))>475.0
            metal9_conn)
    )
    saveDerived(antError23
        "ANT.4.M9: Metal9 area to gate area ratio must be <= 475.0")

)

; procedure for switches CHECK_METAL9_ANT_6
procedure( switchProc24()
    geomConnect(
        via(Via8 metal9_conn metal8_conn)
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError24 var1 &&
            ((area(metal9_conn)+area(metal8_conn)+area(metal7_conn)+area(metal6_conn)+area(metal5_conn)+area(metal4_conn)+area(metal3_conn)+area(metal2_conn)+area(metal1_wo_diode))/if(var1
            var1 1))>1200.0 metal9_conn)
    )
    saveDerived(antError24
        "ANT.6.M1_9: Cumulative Metal1 through Metal9 area to gate area ratio must be <= 1200.0")

)

; procedure for switches CHECK_METAL9_ANT_7
procedure( switchProc25()
    geomConnect(
        via(Via8 metal9_conn metal8_conn)
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError25 var1 && ((area(metal9_conn)/if(var1 var1
            1))-((area(diff_diode)*7500.0)+55000.0))>0.0 metal9_conn)
    )
    saveDerived(antError25
        "ANT.7.M1_9: Cumulative Metal1 through Metal9 area to gate area ratio must be <= 55000 + (diode area * 7500)")

)

; procedure for switches CHECK_POLY_ANT_1
procedure( switchProc26()
    geomConnect(
        via(poly_tap poly_on_field Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError26 var1 && (area(poly_on_field)/if(var1 var1 1))>275.0
            poly_on_field)
    )
    saveDerived(antError26
        "ANT.1: Field Poly area to gate area ratio must be <= 275.0")

)

; procedure for switches CHECK_POLY_ANT_2
procedure( switchProc27()
    geomConnect(
        via(poly_tap poly_on_field Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError27 var1 && (perimeter(poly_on_field)/if(var1 var1
            1))>550.0 poly_on_field)
    )
    saveDerived(antError27
        "ANT.2: Field Poly perimeter to gate area ratio must be <= 550.0")

)

; procedure for switches CHECK_VIA1_ANT_5
procedure( switchProc28()
    geomConnect(
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError28 var1 && (area(Via1)/if(var1 var1 1))>25.0 metal2_conn)
    )
    saveDerived(antError28
        "ANT.5.V1: Via1 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA1_ANT_8
procedure( switchProc29()
    geomConnect(
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError29 var1 && ((area(Via1)/if(var1 var1
            1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal2_conn)
    )
    saveDerived(antError29
        "ANT.8.V1_1: Via1 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA2_ANT_5
procedure( switchProc30()
    geomConnect(
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError30 var1 && (area(Via2)/if(var1 var1 1))>25.0 metal3_conn)
    )
    saveDerived(antError30
        "ANT.5.V2: Via2 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA2_ANT_8
procedure( switchProc31()
    geomConnect(
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError31 var1 && (((area(Via1)+area(Via2))/if(var1 var1
            1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal3_conn)
    )
    saveDerived(antError31
        "ANT.8.V1_2: Cumulative Via1 through Via2 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA3_ANT_5
procedure( switchProc32()
    geomConnect(
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError32 var1 && (area(Via3)/if(var1 var1 1))>25.0 metal4_conn)
    )
    saveDerived(antError32
        "ANT.5.V3: Via3 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA3_ANT_8
procedure( switchProc33()
    geomConnect(
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError33 var1 && (((area(Via1)+area(Via2)+area(Via3))/if(var1
            var1 1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal4_conn)
    )
    saveDerived(antError33
        "ANT.8.V1_3: Cumulative Via1 through Via3 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA4_ANT_5
procedure( switchProc34()
    geomConnect(
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError34 var1 && (area(Via4)/if(var1 var1 1))>25.0 metal5_conn)
    )
    saveDerived(antError34
        "ANT.5.V4: Via4 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA4_ANT_8
procedure( switchProc35()
    geomConnect(
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError35 var1 &&
            (((area(Via1)+area(Via2)+area(Via3)+area(Via4))/if(var1 var1
            1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal5_conn)
    )
    saveDerived(antError35
        "ANT.8.V1_4: Cumulative Via1 through Via4 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA5_ANT_5
procedure( switchProc36()
    geomConnect(
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError36 var1 && (area(Via5)/if(var1 var1 1))>25.0 metal6_conn)
    )
    saveDerived(antError36
        "ANT.5.V5: Via5 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA5_ANT_8
procedure( switchProc37()
    geomConnect(
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError37 var1 &&
            (((area(Via1)+area(Via2)+area(Via3)+area(Via4)+area(Via5))/if(var1
            var1 1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal6_conn)
    )
    saveDerived(antError37
        "ANT.8.V1_5: Cumulative Via1 through Via5 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA6_ANT_5
procedure( switchProc38()
    geomConnect(
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError38 var1 && (area(Via6)/if(var1 var1 1))>25.0 metal7_conn)
    )
    saveDerived(antError38
        "ANT.5.V6: Via6 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA6_ANT_8
procedure( switchProc39()
    geomConnect(
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError39 var1 &&
            (((area(Via1)+area(Via2)+area(Via3)+area(Via4)+area(Via5)+area(Via6))/if(var1
            var1 1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal7_conn)
    )
    saveDerived(antError39
        "ANT.8.V1_6: Cumulative Via1 through Via6 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA7_ANT_5
procedure( switchProc40()
    geomConnect(
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError40 var1 && (area(Via7)/if(var1 var1 1))>25.0 metal8_conn)
    )
    saveDerived(antError40
        "ANT.5.V7: Via7 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA7_ANT_8
procedure( switchProc41()
    geomConnect(
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError41 var1 &&
            (((area(Via1)+area(Via2)+area(Via3)+area(Via4)+area(Via5)+area(Via6)+area(Via7))/if(var1
            var1 1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal8_conn)
    )
    saveDerived(antError41
        "ANT.8.V1_7: Cumulative Via1 through Via7 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

; procedure for switches CHECK_VIA8_ANT_5
procedure( switchProc42()
    geomConnect(
        via(Via8 metal9_conn metal8_conn)
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_wo_diode)
        via(cont_poly metal1_wo_diode Poly)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError42 var1 && (area(Via8)/if(var1 var1 1))>25.0 metal9_conn)
    )
    saveDerived(antError42
        "ANT.5.V8: Via8 area to gate area ratio must be <= 25.0")

)

; procedure for switches CHECK_VIA8_ANT_8
procedure( switchProc43()
    geomConnect(
        via(Via8 metal9_conn metal8_conn)
        via(Via7 metal8_conn metal7_conn)
        via(Via6 metal7_conn metal6_conn)
        via(Via5 metal6_conn metal5_conn)
        via(Via4 metal5_conn metal4_conn)
        via(Via3 metal4_conn metal3_conn)
        via(Via2 metal3_conn metal2_conn)
        via(Via1 metal2_conn metal1_with_diode)
        via(cont_poly metal1_with_diode Poly)
        via(cont_diode metal1_with_diode diff_diode)
    )

    gate=geomStamp(gate Poly)
    drcAntenna(
        var1=area(gate)
        create(antError43 var1 &&
            (((area(Via1)+area(Via2)+area(Via3)+area(Via4)+area(Via5)+area(Via6)+area(Via7)+area(Via8))/if(var1
            var1 1))-((area(diff_diode)*250.0)+1000.0))>0.0 metal9_conn)
    )
    saveDerived(antError43
        "ANT.8.V1_8: Cumulative Via1 through Via8 area to gate area ratio must be <= 1000 + (diode area * 250)")

)

Cont=geomOr(("Cont" "drawing"))

M1Resdum=geomOr(("M1Resdum" "drawing"))

M2Resdum=geomOr(("M2Resdum" "drawing"))

M3Resdum=geomOr(("M3Resdum" "drawing"))

M4Resdum=geomOr(("M4Resdum" "drawing"))

M5Resdum=geomOr(("M5Resdum" "drawing"))

M6Resdum=geomOr(("M6Resdum" "drawing"))

M7Resdum=geomOr(("M7Resdum" "drawing"))

M8Resdum=geomOr(("M8Resdum" "drawing"))

M9Resdum=geomOr(("M9Resdum" "drawing"))

Metal1_d=geomOr(("Metal1" "drawing"))

Metal1_n=geomOr(("Metal1" "net"))

Metal1_p=geomOr(("Metal1" "pin"))

Metal1_slot=geomOr(("Metal1" "slot"))

Metal2_d=geomOr(("Metal2" "drawing"))

Metal2_n=geomOr(("Metal2" "net"))

Metal2_p=geomOr(("Metal2" "pin"))

Metal2_slot=geomOr(("Metal2" "slot"))

Metal3_d=geomOr(("Metal3" "drawing"))

Metal3_n=geomOr(("Metal3" "net"))

Metal3_p=geomOr(("Metal3" "pin"))

Metal3_slot=geomOr(("Metal3" "slot"))

Metal4_d=geomOr(("Metal4" "drawing"))

Metal4_n=geomOr(("Metal4" "net"))

Metal4_p=geomOr(("Metal4" "pin"))

Metal4_slot=geomOr(("Metal4" "slot"))

Metal5_d=geomOr(("Metal5" "drawing"))

Metal5_n=geomOr(("Metal5" "net"))

Metal5_p=geomOr(("Metal5" "pin"))

Metal5_slot=geomOr(("Metal5" "slot"))

Metal6_d=geomOr(("Metal6" "drawing"))

Metal6_n=geomOr(("Metal6" "net"))

Metal6_p=geomOr(("Metal6" "pin"))

Metal6_slot=geomOr(("Metal6" "slot"))

Metal7_d=geomOr(("Metal7" "drawing"))

Metal7_n=geomOr(("Metal7" "net"))

Metal7_p=geomOr(("Metal7" "pin"))

Metal7_slot=geomOr(("Metal7" "slot"))

Metal8_d=geomOr(("Metal8" "drawing"))

Metal8_n=geomOr(("Metal8" "net"))

Metal8_p=geomOr(("Metal8" "pin"))

Metal8_slot=geomOr(("Metal8" "slot"))

Metal9_d=geomOr(("Metal9" "drawing"))

Metal9_n=geomOr(("Metal9" "net"))

Metal9_p=geomOr(("Metal9" "pin"))

Metal9_slot=geomOr(("Metal9" "slot"))

NPNdummy=geomOr(("NPNdummy" "drawing"))

Nimp=geomOr(("Nimp" "drawing"))

Oxide=geomOr(("Oxide" "drawing"))

Pimp=geomOr(("Pimp" "drawing"))

Poly=geomOr(("Poly" "drawing"))

Resdum=geomOr(("Resdum" "drawing"))

Via1=geomOr(("Via1" "drawing"))

Via2=geomOr(("Via2" "drawing"))

Via3=geomOr(("Via3" "drawing"))

Via4=geomOr(("Via4" "drawing"))

Via5=geomOr(("Via5" "drawing"))

Via6=geomOr(("Via6" "drawing"))

Via7=geomOr(("Via7" "drawing"))

Via8=geomOr(("Via8" "drawing"))


; cont_poly=Cont and Poly
cont_poly=geomAnd(Cont Poly)

; cont_antenna=cont_poly and Poly
cont_antenna=geomAnd(Poly cont_poly)

; gate=Poly and Oxide
gate=geomAnd(Oxide Poly)

; nactive=Nimp and Oxide
nactive=geomAnd(Nimp Oxide)

; pactive=Pimp and Oxide
pactive=geomAnd(Oxide Pimp)

; pdiff=pactive andnot Poly
pdiff=geomAndNot(pactive Poly)

; poly_conn=Poly andnot Resdum
poly_conn=geomAndNot(Poly Resdum)

; ndiff=(nactive andnot poly_conn)
ndiff=geomAndNot(nactive poly_conn)

; poly_on_field=Poly andnot Oxide
poly_on_field=geomAndNot(Poly Oxide)

; poly_tap=poly_on_field and Poly
poly_tap=geomAnd(Poly poly_on_field)

; ndiff_conn=ndiff andnot Resdum andnot NPNdummy
L46829=geomAndNot(ndiff Resdum)
ndiff_conn=geomAndNot(L46829 NPNdummy)

; cont_ndiff=Cont and ndiff_conn
cont_ndiff=geomAnd(Cont ndiff_conn)

; pdiff_conn=pdiff andnot Resdum andnot NPNdummy
L12267=geomAndNot(pdiff Resdum)
pdiff_conn=geomAndNot(L12267 NPNdummy)

; cont_pdiff=Cont and pdiff_conn
cont_pdiff=geomAnd(Cont pdiff_conn)

; cont_diode=cont_ndiff or cont_pdiff
cont_diode=geomOr(cont_ndiff cont_pdiff)

; diff_diode=ndiff_conn or pdiff_conn
diff_diode=geomOr(ndiff_conn pdiff_conn)

; Metal1_d_n=if MergePinAndNet Metal1_d or Metal1_n else Metal1_d
ivIf( switch("MergePinAndNet") then
    Metal1_d_n=geomOr(Metal1_d Metal1_n)
else
    Metal1_d_n=Metal1_d
)


; Metal1=Metal1_d_n or Metal1_p
Metal1=geomOr(Metal1_d_n Metal1_p)

; metal1_conn=(Metal1 andnot Metal1_slot) andnot M1Resdum
L32159=geomAndNot(Metal1 Metal1_slot)
metal1_conn=geomAndNot(L32159 M1Resdum)

; Metal2_d_n=if MergePinAndNet Metal2_d or Metal2_n else Metal2_d
ivIf( switch("MergePinAndNet") then
    Metal2_d_n=geomOr(Metal2_d Metal2_n)
else
    Metal2_d_n=Metal2_d
)


; Metal2=Metal2_d_n or Metal2_p
Metal2=geomOr(Metal2_d_n Metal2_p)

; metal2_conn=(Metal2 andnot Metal2_slot) andnot M2Resdum
L6015=geomAndNot(Metal2 Metal2_slot)
metal2_conn=geomAndNot(L6015 M2Resdum)

; Metal3_d_n=if MergePinAndNet Metal3_d or Metal3_n else Metal3_d
ivIf( switch("MergePinAndNet") then
    Metal3_d_n=geomOr(Metal3_d Metal3_n)
else
    Metal3_d_n=Metal3_d
)


; Metal3=Metal3_d_n or Metal3_p
Metal3=geomOr(Metal3_d_n Metal3_p)

; metal3_conn=(Metal3 andnot Metal3_slot) andnot M3Resdum
L79871=geomAndNot(Metal3 Metal3_slot)
metal3_conn=geomAndNot(L79871 M3Resdum)

; Metal4_d_n=if MergePinAndNet Metal4_d or Metal4_n else Metal4_d
ivIf( switch("MergePinAndNet") then
    Metal4_d_n=geomOr(Metal4_d Metal4_n)
else
    Metal4_d_n=Metal4_d
)


; Metal4=Metal4_d_n or Metal4_p
Metal4=geomOr(Metal4_d_n Metal4_p)

; metal4_conn=(Metal4 andnot Metal4_slot) andnot M4Resdum
L53727=geomAndNot(Metal4 Metal4_slot)
metal4_conn=geomAndNot(L53727 M4Resdum)

; Metal5_d_n=if MergePinAndNet Metal5_d or Metal5_n else Metal5_d
ivIf( switch("MergePinAndNet") then
    Metal5_d_n=geomOr(Metal5_d Metal5_n)
else
    Metal5_d_n=Metal5_d
)


; Metal5=Metal5_d_n or Metal5_p
Metal5=geomOr(Metal5_d_n Metal5_p)

; metal5_conn=(Metal5 andnot Metal5_slot) andnot M5Resdum
L27583=geomAndNot(Metal5 Metal5_slot)
metal5_conn=geomAndNot(L27583 M5Resdum)

; Metal6_d_n=if MergePinAndNet Metal6_d or Metal6_n else Metal6_d
ivIf( switch("MergePinAndNet") then
    Metal6_d_n=geomOr(Metal6_d Metal6_n)
else
    Metal6_d_n=Metal6_d
)


; Metal6=Metal6_d_n or Metal6_p
Metal6=geomOr(Metal6_d_n Metal6_p)

; metal6_conn=(Metal6 andnot Metal6_slot) andnot M6Resdum
L65857=geomAndNot(Metal6 Metal6_slot)
metal6_conn=geomAndNot(L65857 M6Resdum)

; Metal7_d_n=if MergePinAndNet Metal7_d or Metal7_n else Metal7_d
ivIf( switch("MergePinAndNet") then
    Metal7_d_n=geomOr(Metal7_d Metal7_n)
else
    Metal7_d_n=Metal7_d
)


; Metal7=Metal7_d_n or Metal7_p
Metal7=geomOr(Metal7_d_n Metal7_p)

; metal7_conn=(Metal7 andnot Metal7_slot) andnot M7Resdum
L92001=geomAndNot(Metal7 Metal7_slot)
metal7_conn=geomAndNot(L92001 M7Resdum)

; Metal8_d_n=if MergePinAndNet Metal8_d or Metal8_n else Metal8_d
ivIf( switch("MergePinAndNet") then
    Metal8_d_n=geomOr(Metal8_d Metal8_n)
else
    Metal8_d_n=Metal8_d
)


; Metal8=Metal8_d_n or Metal8_p
Metal8=geomOr(Metal8_d_n Metal8_p)

; metal8_conn=(Metal8 andnot Metal8_slot) andnot M8Resdum
L18145=geomAndNot(Metal8 Metal8_slot)
metal8_conn=geomAndNot(L18145 M8Resdum)

; Metal9_d_n=if MergePinAndNet Metal9_d or Metal9_n else Metal9_d
ivIf( switch("MergePinAndNet") then
    Metal9_d_n=geomOr(Metal9_d Metal9_n)
else
    Metal9_d_n=Metal9_d
)


; Metal9=Metal9_d_n or Metal9_p
Metal9=geomOr(Metal9_d_n Metal9_p)

; metal9_conn=(Metal9 andnot Metal9_slot) andnot M9Resdum
L44289=geomAndNot(Metal9 Metal9_slot)
metal9_conn=geomAndNot(L44289 M9Resdum)

; metal1_with_diode=(metal1_conn interact > 1 diff_diode) or (metal1_conn interact
;  (diff_diode area >= 0.1))
L90713=geomButtOrOver(metal1_conn diff_diode keep>1)
L28904=drc(diff_diode area>=0.1)
L77036=geomButtOrOver(metal1_conn L28904)
metal1_with_diode=geomOr(L77036 L90713)

; metal1_wo_diode=metal1_conn andnot metal1_with_diode
metal1_wo_diode=geomAndNot(metal1_conn metal1_with_diode)


ivIf( switch("CHECK_CONT_ANT_3") then switchProc0() )

ivIf( switch("CHECK_METAL1_ANT_4") then switchProc1() )

ivIf( switch("CHECK_METAL1_ANT_7") then switchProc2() )

ivIf( switch("CHECK_METAL2_ANT_4") then switchProc3() )

ivIf( switch("CHECK_METAL2_ANT_7") then switchProc4() )

ivIf( switch("CHECK_METAL3_ANT_4") then switchProc5() )

ivIf( switch("CHECK_METAL3_ANT_6") then switchProc6() )

ivIf( switch("CHECK_METAL3_ANT_7") then switchProc7() )

ivIf( switch("CHECK_METAL4_ANT_4") then switchProc8() )

ivIf( switch("CHECK_METAL4_ANT_6") then switchProc9() )

ivIf( switch("CHECK_METAL4_ANT_7") then switchProc10() )

ivIf( switch("CHECK_METAL5_ANT_4") then switchProc11() )

ivIf( switch("CHECK_METAL5_ANT_6") then switchProc12() )

ivIf( switch("CHECK_METAL5_ANT_7") then switchProc13() )

ivIf( switch("CHECK_METAL6_ANT_4") then switchProc14() )

ivIf( switch("CHECK_METAL6_ANT_6") then switchProc15() )

ivIf( switch("CHECK_METAL6_ANT_7") then switchProc16() )

ivIf( switch("CHECK_METAL7_ANT_4") then switchProc17() )

ivIf( switch("CHECK_METAL7_ANT_6") then switchProc18() )

ivIf( switch("CHECK_METAL7_ANT_7") then switchProc19() )

ivIf( switch("CHECK_METAL8_ANT_4") then switchProc20() )

ivIf( switch("CHECK_METAL8_ANT_6") then switchProc21() )

ivIf( switch("CHECK_METAL8_ANT_7") then switchProc22() )

ivIf( switch("CHECK_METAL9_ANT_4") then switchProc23() )

ivIf( switch("CHECK_METAL9_ANT_6") then switchProc24() )

ivIf( switch("CHECK_METAL9_ANT_7") then switchProc25() )

ivIf( switch("CHECK_POLY_ANT_1") then switchProc26() )

ivIf( switch("CHECK_POLY_ANT_2") then switchProc27() )

ivIf( switch("CHECK_VIA1_ANT_5") then switchProc28() )

ivIf( switch("CHECK_VIA1_ANT_8") then switchProc29() )

ivIf( switch("CHECK_VIA2_ANT_5") then switchProc30() )

ivIf( switch("CHECK_VIA2_ANT_8") then switchProc31() )

ivIf( switch("CHECK_VIA3_ANT_5") then switchProc32() )

ivIf( switch("CHECK_VIA3_ANT_8") then switchProc33() )

ivIf( switch("CHECK_VIA4_ANT_5") then switchProc34() )

ivIf( switch("CHECK_VIA4_ANT_8") then switchProc35() )

ivIf( switch("CHECK_VIA5_ANT_5") then switchProc36() )

ivIf( switch("CHECK_VIA5_ANT_8") then switchProc37() )

ivIf( switch("CHECK_VIA6_ANT_5") then switchProc38() )

ivIf( switch("CHECK_VIA6_ANT_8") then switchProc39() )

ivIf( switch("CHECK_VIA7_ANT_5") then switchProc40() )

ivIf( switch("CHECK_VIA7_ANT_8") then switchProc41() )

ivIf( switch("CHECK_VIA8_ANT_5") then switchProc42() )

ivIf( switch("CHECK_VIA8_ANT_8") then switchProc43() )

)
