// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module trans_ld_100tx ( ibias_rext_50u,ibias_100tx_100u,
ibias_100tx_400u,neg_out,VDD,pos_out,siddq,TX_on,VSS,MLT3ENC_DATA ); 

input   ibias_rext_50u;
input   ibias_100tx_100u;
input  
 ibias_100tx_400u;
output   neg_out;
input   VDD;
output   pos_out;

input   siddq;
input   TX_on;
input   VSS;
input [1:0]  MLT3ENC_DATA;

 
 
 
gpdk090_nmoscap2v #(.m(1 * 25), .l(12.87u), .w(12.82u)) (*
integer 
library_binding = "gpdk090";
integer passed_mfactor = "m";
integer 
elaboration_binding = "C0[9:0]";
 *)
C0_9 ( VSS, VDD, VSS, VSS ),
  C0_8 ( VSS, VDD, VSS, VSS ),
  C0_7 ( VSS, VDD, VSS, VSS ),
  C0_6 ( VSS, VDD, VSS, VSS ),
  C0_5 ( VSS, VDD, VSS, VSS ),
  C0_4 ( VSS, VDD, VSS, VSS ),
  C0_3 ( VSS, VDD, VSS, VSS ),
  C0_2 ( VSS, VDD, VSS, VSS ),
  C0_1 ( VSS, VDD, VSS, VSS ),
  C0_0 ( VSS, VDD, VSS, VSS );
 
inv_16x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I2 ( .Y( net64 ), .A( TX_on ) );
 
trans_ld_100TX_current_mirror (*
integer library_binding = "ether";

 *)
I24 ( .MLT3( MLT3ENC_DATA[1:0] ), .vbias( net54 ), .neg_out( 
neg_out ), .VDD( VDD ), .pos_out( pos_out ), .siddq( net64 ), .switch_vbias( 
net59 ), .VSS( VSS ) );
 
trans_ld_100tx_bias (*
integer library_binding = "ether";
 *)
I29 ( .ibias_rext_50u( 
ibias_rext_50u ), .ibias_100tx_100u( ibias_100tx_100u ), .FBI( net067 ), 
.VDD( VDD ), .siddq( siddq ), .tx_vbias( net54 ), .switch_vbias( net59 ), 
.TX_on( TX_on ), .VSS( VSS ), .FBO( net067 ), .tx_ibias_400u( 
ibias_100tx_400u ) );

endmodule
