// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module anlg_cntl ( PHASE_IN,TEST_MODE,PHASE_125,XTAL25,TXER,X_160,
SIDDQ,TP_DISC_1p0,RX10_PRESENT_2p5,MR_SQUELCH_RANGE_1p0,MLT3_TDATA_2p5,
ADC_DIS_2p5,ADC_TEST_2p5,SLICER_OUT_2p5,X10_DIS_2p5,BASE10_DIS,
TP_DISC_2p5,BASE100TX_DIS,PHASE_250,RX10_PRESENT_1p0,TX_AMPTRIM_1p0,
POS_DETECT_1p0,MLT3_TDATA_1p0,SLICER_OUT_1p0,VDDRX,MR_SQUELCH_DISB_2p5,
NEG_DETECT_2p5,NEG_DETECT_1p0,RESETN,RCLK125_TST_SEL,VDD,
MR_SQUELCH_DISB_1p0,X_125,PLL_160_IN,BASEFX_DIS,VDDTX,RCLK125_TST,
GNDRX,MR_SQUELCH_RANGE_2p5,XTAL25_IN,POS_DETECT_2p5,AEQ_DIS_2p5,
BLW_DIS_2p5,TX100_DIS_2p5,TX_SLOPETRIM_1p0,GND,GNDTX ); 

input [10:0]  PHASE_IN;
input [2:0]  TEST_MODE;
output [10:0] 
 PHASE_125;
output   XTAL25;
input   TXER;
output   X_160;
input  
 SIDDQ;
input   TP_DISC_1p0;
output   RX10_PRESENT_2p5;
input [1:0] 
 MR_SQUELCH_RANGE_1p0;
output [1:0]  MLT3_TDATA_2p5;
output  
 ADC_DIS_2p5;
output   ADC_TEST_2p5;
input   SLICER_OUT_2p5;
output  
 X10_DIS_2p5;
input   BASE10_DIS;
output   TP_DISC_2p5;
input  
 BASE100TX_DIS;
output [10:0]  PHASE_250;
input   RX10_PRESENT_1p0;

input [1:0]  TX_AMPTRIM_1p0;
output   POS_DETECT_1p0;
input [1:0] 
 MLT3_TDATA_1p0;
output   SLICER_OUT_1p0;
input   VDDRX;
output  
 MR_SQUELCH_DISB_2p5;
input   NEG_DETECT_2p5;
output  
 NEG_DETECT_1p0;
input   RESETN;
output   RCLK125_TST_SEL;
input  
 VDD;
input   MR_SQUELCH_DISB_1p0;
output   X_125;
input  
 PLL_160_IN;
input   BASEFX_DIS;
input   VDDTX;
output   RCLK125_TST;

input   GNDRX;
output [1:0]  MR_SQUELCH_RANGE_2p5;
input   XTAL25_IN;

input   POS_DETECT_2p5;
output   AEQ_DIS_2p5;
output   BLW_DIS_2p5;

output   TX100_DIS_2p5;
input [1:0]  TX_SLOPETRIM_1p0;
input   GND;

input   GNDTX;

wire [1:0] TX_AMPTRIM_2p5;
wire [1:0] TX_SLOPETRIM_2p5;
 
 
gpdk090_nmoscap2v #(.m(16 * 4), .l(11.5u), .w(11.5u)) (*
integer 
library_binding = "gpdk090";
integer passed_mfactor = "m";
 *)
C1 ( 
GND, VDD, GND, GND );
 
clock_buffer #(.usim_opt("sim_mod=df acc=2")) (*
integer 
library_binding = "ether";
integer cds_net_set[0:1] = { "DVDD","DVSS"
 };
integer DVDD = "VDD";
integer DVSS = "GND";
 *)
I38 ( .IN( TXER ), 
.OUT( RCLK125_TST ) );
 
top_1_port_1p0_to_2p5 #(.d2a_tr("100p"), .ieIO("output"), .a2d_v0("0.5"),
 .d2a_tf("100p"), .a2d_v1("0.8"), .a2d_tx("100p"), .d2a_vh("2.5"), .usim_opt("sim_mod=ms acc=2")) 
(*
integer library_binding = "ether";
 *)
I60 ( .RX10_PRESENT_2p5( 
RX10_PRESENT_2p5 ), .TP_DISC_1p0( TP_DISC_1p0 ), .MLT3_TDATA_2p5( 
MLT3_TDATA_2p5[1:0] ), .MR_SQUELCH_RANGE_1p0( 
MR_SQUELCH_RANGE_1p0[1:0] ), .TP_DISC_2p5( TP_DISC_2p5 ), .RX10_PRESENT_1p0( 
RX10_PRESENT_1p0 ), .TX_AMPTRIM_1p0( TX_AMPTRIM_1p0[1:0] ), .MLT3_TDATA_1p0( 
MLT3_TDATA_1p0[1:0] ), .MR_SQUELCH_DISB_2p5( MR_SQUELCH_DISB_2p5 ), .VDD_1p0( 
VDD ), .MR_SQUELCH_DISB_1p0( MR_SQUELCH_DISB_1p0 ), .MR_SQUELCH_RANGE_2p5( 
MR_SQUELCH_RANGE_2p5[1:0] ), .TX_AMPTRIM_2p5( TX_AMPTRIM_2p5[1:0] ), .VDD_2p5( 
VDDRX ), .VSS( GND ), .TX_SLOPETRIM_1p0( TX_SLOPETRIM_1p0[1:0] ), .TX_SLOPETRIM_2p5( 
TX_SLOPETRIM_2p5[1:0] ) );
 
top_1_port_2p5_to1p0 #(.ieIO("input"), .d2a_tr("100p"), .a2d_v0("0.5"),
 .d2a_tf("100p"), .d2a_vh("2.5"), .a2d_v1("0.8"), .a2d_tx("100p"), .usim_opt("sim_mod=ms acc=2")) 
(*
integer library_binding = "ether";
 *)
I59 ( .SLICER_OUT_2p5( 
SLICER_OUT_2p5 ), .POS_DETECT_1p0( POS_DETECT_1p0 ), .SLICER_OUT_1p0( 
SLICER_OUT_1p0 ), .VDD_1p0( VDD ), .NEG_DETECT_2p5( NEG_DETECT_2p5 ), 
.NEG_DETECT_1p0( NEG_DETECT_1p0 ), .POS_DETECT_2p5( POS_DETECT_2p5 ), 
.VDD_2p5( VDDRX ), .VSS( GND ) );
 
top_buff (*
integer library_binding = "ether";
integer cds_net_set
[0:0] = { "DVDD" };
integer DVDD = "VDD";
 *)
I49 ( .PHASE_IN( 
PHASE_IN[10:0] ), .PHASE_125( PHASE_125[10:0] ), .XTAL25( XTAL25 ), .X_160( 
X_160 ), .PHASE_250( PHASE_250[10:0] ), .VDDRX( VDDRX ), .RESETN( 
RESETN ), .VDD( VDD ), .X_125( X_125 ), .PLL_160_IN( PLL_160_IN ), .VDDTX( 
VDDTX ), .GNDRX( GNDRX ), .XTAL25_IN( XTAL25_IN ), .GND( GND ), .GNDTX( 
GNDTX ) );
 
analog_test_dec #(.d2a_tr("100p"), .ieIO("output"), .d2a_tf("100p"), .d2a_vh("1")) 
(*
integer library_binding = "ether";
integer cds_net_set[0:1] = { 
"VDD","VSS" };
integer VDD = "VDD";
integer VSS = "GND";
 *)
I35 ( .TEST_MODE( 
TEST_MODE[2:0] ), .AEQ_DIS( AEQ_DIS_1p0 ), .BLW_DIS( BLW_DIS_1p0 ), .SIDDQ( 
SIDDQ_1p0 ), .BASE100X_DIS( BASE100TX_DIS ), .FX_DIS( FX_DIS ), .ADC_DIS( 
ADC_DIS_1p0 ), .BASE10X_DIS( BASE10_DIS ), .RCLK125_TST_SEL( 
RCLK125_TST_SEL ), .BASEFX_DIS( BASEFX_DIS ), .X10_DIS( X10_DIS_1p0 ), 
.ADC_TEST( ADC_TEST_1p0 ), .TX100_DIS( TX100_DIS_1p0 ) );
 
analog_test_dec_lvshift (*
integer library_binding = "ether";
 *)
I45
 ( .TX100_DIS_1p0( TX100_DIS_1p0 ), .ADC_DIS_2p5( ADC_DIS_2p5 ), .ADC_TEST_2p5( 
ADC_TEST_2p5 ), .AVDD_2p5V( VDDRX ), .X10_DIS_2p5( X10_DIS_2p5 ), .DVDD( 
VDD ), .ADC_TEST_1p0( ADC_TEST_1p0 ), .AEQ_DIS_1p0( AEQ_DIS_1p0 ), .X10_DIS_1p0( 
X10_DIS_1p0 ), .ADC_DIS_1p0( ADC_DIS_1p0 ), .AEQ_DIS_2p5( AEQ_DIS_2p5 ), 
.BLW_DIS_2p5( BLW_DIS_2p5 ), .TX100_DIS_2p5( TX100_DIS_2p5 ), .GND( 
GND ), .BLW_DIS_1p0( BLW_DIS_1p0 ) );
 
level_shifter_2p5_1p0 (*
integer library_binding = "ether";
 *)
I46 ( 
.IN( SIDDQ ), .VDD_1p0( VDD ), .VDD_2p5( VDDRX ), .OUT( SIDDQ_1p0 ), .VSS( 
GND ) );

endmodule
