// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module blw_dac_inv_eqdelay ( dvdd,dgnd,in,out,xout ); 

inout   dvdd;
inout   dgnd;
input   in;
output   out;
output   xout;

 
 
 
gpdk090_pmos2v #(.ps(8.2u), .m(1 * 1), .as(2.1p), .l(280.0n), .pd(8.2u),
 .ad(2.1p), .w(3.5u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM0 ( net23, net30, dvdd, dvdd );
gpdk090_pmos2v #(.ps(8.2u), .m(1 * 1), .as(2.1p), .l(280.0n), .pd(8.2u),
 .ad(2.1p), .w(3.5u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM1 ( net21, dgnd, net26, dvdd );
 
gpdk090_nmos2v #(.ps(3.53u), .m(1 * 1), .as(699f), .l(280.0n), .pd(3.53u),
 .ad(699f), .w(1.165u)) (*
integer library_binding = "gpdk090";

integer passed_mfactor = "m";
 *)
NM1 ( net26, dvdd, net21, dgnd );
gpdk090_nmos2v #(.ps(3.53u), .m(1 * 1), .as(699f), .l(280.0n), .pd(3.53u),
 .ad(699f), .w(1.165u)) (*
integer library_binding = "gpdk090";

integer passed_mfactor = "m";
 *)
NM0 ( net23, net30, dgnd, dgnd );
 
inv_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "dvdd";
integer DVSS
 = "dgnd";
 *)
I19 ( .Y( xout ), .A( net23 ) );
inv_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "dgnd";
integer DVDD
 = "dvdd";
 *)
I20 ( .Y( out ), .A( net21 ) );
inv_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "dvdd";
integer DVSS
 = "dgnd";
 *)
I2 ( .Y( net26 ), .A( in ) );
inv_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "dgnd";
integer DVDD
 = "dvdd";
 *)
I0 ( .Y( net30 ), .A( in ) );

endmodule
