// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module Bias_I_50u_Rext_cell_port ( SIDDQ,Iout,Pcasc,VDD,Pbias,VSS ); 

input   SIDDQ;
output   Iout;
input   Pcasc;
input   VDD;
input  
 Pbias;
input   VSS;

 
 
gpdk090_nmos2v #(.ps(3.2u), .m(1 * 1), .as(600f), .l(280.0n), .pd(3.2u),
 .ad(600f), .w(1u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
NM5 ( Iout, SIDDQ, VSS, VSS );
 
gpdk090_pmos2v #(.ps(30.9u), .m(1 * 4), .as(9p), .l(2.5u), .pd(20.6u),
 .ad(6p), .w(20u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM198 ( net022, Pbias, VDD, VDD );
gpdk090_pmos2v #(.ps(15.9u), .m(1 * 4), .as(4.5p), .l(1u), .pd(10.6u),
 .ad(3p), .w(10u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM199 ( Iout, Pcasc, net022, VDD );

endmodule
