// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module Bias_bandgap ( SIDDQ,TRIM,VBG,VDD,AC_IN,VSS,AC_OUT ); 

input   SIDDQ;
input [3:0]  TRIM;
output   VBG;
input   VDD;
input  
 AC_IN;
input   VSS;
output   AC_OUT;

wire [15:0] SEL;
 
wire (*
integer inh_conn_prop_name = "bulk_n";
integer 
inh_conn_def_value = "cds_globals.\\gnd! ";
 *)
\bulk_n_gnd! ;
 
 
DEC_4to16 (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I2 ( .S( TRIM[3:0] ), .OUT( SEL[15:0] ) );
 
Bias_bdgp_amp (*
integer library_binding = "ether";
 *)
I0 ( .INn( INn ), 
.SEL( SEL[15:0] ), .VBG( Vbg_int ), .VDD( VDD ), .INp( INp ), .PD( 
SIDDQ ), .OUT( AC_OUT ), .VSS( VSS ) );
 
gpdk090_vpnp5 #(.area(25.0), .m(16)) (*
integer library_binding
 = "gpdk090";
integer passed_mfactor = "m";
 *)
Q2 ( VSS, VSS, Vbe_Q5, 
\bulk_n_gnd!  );
gpdk090_vpnp5 #(.area(25.0), .m(2)) (*
integer library_binding
 = "gpdk090";
integer passed_mfactor = "m";
 *)
Q1 ( VSS, VSS, INn, 
\bulk_n_gnd!  );
 
gpdk090_resnsppoly #(.w(2u), .r(19.9973K), .l(99.9743u)) (*
integer 
library_binding = "gpdk090";
 *)
R3 ( Vbg_int, VBG, VDD );
gpdk090_resnsppoly #(.w(2u), .r(42.1229K), .l(210.62u)) (*
integer 
library_binding = "gpdk090";
 *)
R0 ( Vbg_int, INn, Vbg_int );
gpdk090_resnsppoly #(.w(2u), .r(42.1229K), .l(210.62u)) (*
integer 
library_binding = "gpdk090";
 *)
R1 ( Vbg_int, INp, Vbg_int );
gpdk090_resnsppoly #(.w(2u), .r(4.53428K), .l(22.66u)) (*
integer 
library_binding = "gpdk090";
 *)
R2 ( INp, Vbe_Q5, Vbg_int );
 
gpdk090_pmos2v #(.ps(6.2u), .m(1 * 1), .as(1.5p), .l(500n), .pd(6.2u),
 .ad(1.5p), .w(2.5u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM0 ( Vbg_int, AC_IN, VDD, VDD );
 
gpdk090_nmoscap2v #(.m(1 * 8), .l(14.39u), .w(14.335u)) (*
integer 
library_binding = "gpdk090";
integer passed_mfactor = "m";
 *)
C0 ( 
VSS, VBG, VSS, VSS );
 
capacitor #(.c(5p)) (*
integer library_binding = "analogLib";
 *)
C1
 ( AC_OUT, VSS );

endmodule
