// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module PI_interp_block ( IN,Tap,VDD,OUT,VSS ); 

input [3:0]  IN;
output [1:0]  Tap;
input   VDD;
output [6:0]  OUT;

input   VSS;

 
 
 
PI_interp_tap_cell (*
integer library_binding = "ether";
 *)
I16 ( .VDD( 
VDD ), .TAP( { net115,net108 } ), .OUT( OUT[3] ), .VSS( VSS ) );
 
PI_interp_cell (*
integer library_binding = "ether";
 *)
I9 ( .IN( 
IN[3:2] ), .Tap( { Tap[1],net115 } ), .VDD( VDD ), .OUT( OUT[6:4] ), .VSS( 
VSS ) );
PI_interp_cell (*
integer library_binding = "ether";
 *)
I8 ( .IN( 
IN[1:0] ), .Tap( { net108,Tap[0] } ), .VDD( VDD ), .OUT( OUT[2:0] ), .VSS( 
VSS ) );

endmodule
