// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module analog_test_dec_lvshift ( TX100_DIS_1p0,ADC_DIS_2p5,
ADC_TEST_2p5,AVDD_2p5V,X10_DIS_2p5,DVDD,ADC_TEST_1p0,X10_DIS_1p0,
AEQ_DIS_1p0,ADC_DIS_1p0,AEQ_DIS_2p5,BLW_DIS_2p5,TX100_DIS_2p5,GND,
BLW_DIS_1p0 ); 

input   TX100_DIS_1p0;
output   ADC_DIS_2p5;
output   ADC_TEST_2p5;

input   AVDD_2p5V;
output   X10_DIS_2p5;
input   DVDD;
input  
 ADC_TEST_1p0;
input   X10_DIS_1p0;
input   AEQ_DIS_1p0;
input  
 ADC_DIS_1p0;
output   AEQ_DIS_2p5;
output   BLW_DIS_2p5;
output  
 TX100_DIS_2p5;
input   GND;
input   BLW_DIS_1p0;

 
 
 
level_shifter_1p0_2p5_inh (*
integer library_binding = "ether";
 *)
I9
 ( .IN( TX100_DIS_1p0 ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( 
TX100_DIS_2p5 ), .VSS( GND ) );
level_shifter_1p0_2p5_inh (*
integer library_binding = "ether";
 *)
I4
 ( .IN( X10_DIS_1p0 ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( 
X10_DIS_2p5 ), .VSS( GND ) );
level_shifter_1p0_2p5_inh (*
integer library_binding = "ether";
 *)
I3
 ( .IN( BLW_DIS_1p0 ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( 
BLW_DIS_2p5 ), .VSS( GND ) );
level_shifter_1p0_2p5_inh (*
integer library_binding = "ether";
 *)
I2
 ( .IN( AEQ_DIS_1p0 ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( 
AEQ_DIS_2p5 ), .VSS( GND ) );
level_shifter_1p0_2p5_inh (*
integer library_binding = "ether";
 *)
I1
 ( .IN( ADC_TEST_1p0 ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( 
ADC_TEST_2p5 ), .VSS( GND ) );
level_shifter_1p0_2p5_inh (*
integer library_binding = "ether";
 *)

I10 ( .IN( ADC_DIS_1p0 ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( 
ADC_DIS_2p5 ), .VSS( GND ) );

endmodule
