// Verilog-AMS cds_globals module for top-level cell:
//      ether_sims/adc_top_sim.
// Generated by AMS.
// Cadence Design Systems, Inc.

`include "disciplines.vams"

module cds_globals;

// Global Signals
    wire \VDD! ;
    wire \VSS! ;
    electrical \gnd! ;
    ground \gnd! ;

// Design Variables
    dynamicparam real basefx_dis = dvdd;
    dynamicparam real base100tx_dis = 0;
    dynamicparam real clk_freq = 125e6;
    dynamicparam real clk_slew = 100p;
    dynamicparam real Cout = 100f;
    dynamicparam real dvdd = 1;
    dynamicparam real in_freq = 56.64e6;
    dynamicparam real in_freq_ampl = 0.2;
    dynamicparam real in_freq_dc = 0.765;
    dynamicparam real isr_100u = 97u;
    dynamicparam real siddq = 0;
    dynamicparam real test_enable = 0;
    dynamicparam real vdd = 2.375;

endmodule
