File name:      README
Purpose:        The basic usage of various connection rules and modules
                of the AMS Simulator.

Revision history:
		Ronald Vogelsong (10/31/02)
		Sudip Chakrabarti (12/30/02)
		Ronald Vogelsong (2/09/03), for PCR 553536, etc.
		Ronald Vogelsong (3/12/04) added supply sensitive formats
		Junwei Hou (1/25/06) added the full fast connect modules
                                     and revised this usage guide
		Junwei Hou (4/18/06) map digital X/Z to analog 0 by default
                                     in the full fast connect modules

DESCRIPTIONS OF CONNECT RULES:
==============================
Supply        Complete            Full Fast                Basic
-------   |   ------------------  -----------------------  ------------------
 5 volt   |   ConnRules_5V_full   ConnRules_5V_full_fast   ConnRules_5V_basic
 3 volt   |   ConnRules_3V_full   ConnRules_3V_full_fast   ConnRules_3V_basic
1.8 volt  |   ConnRules_18V_full  ConnRules_18V_full_fast  ConnRules_18V_basic
<default> |   ConnRules_full      ConnRules_full_fast      ConnRules_basic
SuppSens  |   ConnRules_ss_full   

The "complete" connection rules (*_full) enable reasonable modeling of
problems that can occur across an analog/digital boundary:  analog
loading effects can slow a logic transition; heavy loading can pull a
nominally high logic signal down to X or to low, which will feed back to
the digital side of the connect module. Note that for the full L2E model,
a change in the logic causes the analog voltage to ramp, and the change
in that analog voltage defines the digital value fed back, so there will 
typically be a delay of at least 2/3 of Trise before the digital side
sees the results of the digital input change. The "complete" rules
are compised of connect modules L2E, E2L, and Bidir.

The "full fast" connection rules (*_full_fast) are designed for better
simulation performance while maintaining similar accuracy as that of
the "complete" rules. The main functional difference between the two 
sets of rules are that "complete" rules consider analog loading effect
feedback to digital on all connections across the analog/digital boundary,
while "full fast" rules only do this on user selected connections
(defined as inout port). The "full fast" rules simply map digital X/Z to
analog 0 (by default) and have more efficient analog signal noise
filtering, among other features. These are described in more details
in the comprised connect modules L2E_2, E2L_2, and Bidir_2.

The "basic" rules (*_basic) provides simple two-level digital to analog
conversion (L2E_0,E2L_0), which results in the minimum overhead to provide
the basic functionality of analog to digital conversion.  This of course
assumes that there are no issues with X or Z signals at the interfaces.
This is similar to using the simplest interface elements used in a
spectreVerilog simulation.  Note that the simplified bidirectional module
described above (Bidir_0) is also included in these rules files, so that
simulations with explicitly bidirectional connections at the interface
can still be simulated.  These modules should simulate slightly faster
than the midrange cells, due to the L2E_0 output being constant resistance
and the E2L_0 only checking two rather than four threshold crossings per
cycle.

The "default" rules (with no voltage level specified) just use all the
default parameters specified in the connection modules themselves rather
than specifying values in the rules definition.  This format can be useful
if you modify the connect module parameters themselves to match a
particular case rather than defining a separate rules definition for them.
The specification of these rules is included at the bottom of the
"ConnRules18.vams" file.

The "supply sensitive" rules (*_ss_*) have the same capabilities as
the full or mid sets, but read their supply voltage input using the
supplySensitivity constructs.  There are two standard modes of operation
supported:
1) If the cells in the system are defined with supplySensitivity and
   groundSensitivity properties on their digital input and output pins,
   the connect modules will inherit those parameters from the digital pins
   they are connected to -- provided that detailed discipline resolution
   is used during elaboration (ncelab -dres).
2) Otherwise, the default global node names specified in the connect
   module code (specified as vdd! and vss! here) will be used to determine
   the supplies to reference.



Other Available Connect Rules:
-------------------------------
Supply        Midrange           
-------   |   ------------------
 5 volt   |   ConnRules_5V_mid 
 3 volt   |   ConnRules_3V_mid 
1.8 volt  |   ConnRules_18V_mid
<default> |   ConnRules_mid    
SuppSens  |   ConnRules_ss_mid 

The "midrange" rules (*_mid) use the complete elect-to-logic connect
module (E2L) with the simplified logic-to-elect module (L2E_1).  It has
similar logic level handling capability, but does not include the analog
feedback effects.  Thus when an L2E module is driving a heavy load, the
loading effects will be visible on the analog side but will not be fed
back to the equivalent logic pin associated with that node.  This is
actually similar to the spectreVerilog (Verimix) interface elements in
operation, as they did not have the feedback capability.  The simplified
bidirectional module (Bidir_0) is included in these rule sets, which acts as
the L2E_1 module when the logic is 0,1,or X, but switches to E2L operation
whenever the logic signal goes to Z.  These modules should simulate
somewhat faster than the complete set, as the L2E_1 model doesn't have
to check for threshold crossings on the analog output signals.


DESCRIPTIONS OF CONNECT MODULES:
================================

Complete connect modules:
--------------------------
E2L	full elec-to-logic conversion:
 - converts analog voltage to logic level of 0, X, or 1.
 - suppresses X output on normal transitions (digital goes to X after tx delay).
L2E	full logic-to-elec conversion:
 - drives electrical pin with separate voltage & impedance levels for 0,1,X,Z.
 - includes separate rise times for up, down, and Z transitions
 - actual analog level drives digital side using E2L conversion format, so 
   that any conflict on the analog side is properly reflected back to digital.
Bidir	full bidirectional conversion:
 - identical to L2E module, but defined with bidirectional pins.
E2L_ss, L2E_ss, Bidir_ss   Supply sensitive versions of above modules

Full fast connect modules:
--------------------------
E2L_2	full elec-to-logic conversion:
 - converts analog voltage to logic level of 0, X, or 1.
 - suppresses X output on normal transitions (digital goes to X after tx delay).
 _ with improved hysteresis setup for efficient noise (within vtol) filtering.
L2E_2	full logic-to-elec conversion but with no analog loading feedback:
 - drives electrical pin with separate voltage & impedance levels for 0,1,X,Z.
 - maps initial digital Z/X to analog high-impedance ground-voltage.
 - logic inputs directly define logic level (no feedback from analog)
Bidir_2 full bidirectional conversion:
 - combines the functionalities of both E2L_2 and L2E_2
 - can be used for logic-to-elec conversion with ability of accurate
   feedback of the actual analog loading level to the digital receiver

Simplified connect modules:
--------------------------
E2L_0	simple elec-to-logic conversion
 - defines two level logic output based on two electrical thresholds
L2E_0	simple logic-to-elec conversion
 - defines two level electrical output based on logic input
 - logic inputs directly define logic level (no feedback from analog)
L2E_1	mid level logic-to-elec conversion
 - defines four level electrical output with reasonable impedances for 0,1,X,Z
 - logic inputs directly define logic level (no feedback from analog)
Bidir_0	simple bidirectional conversion
 - Acts as L2E_1 when logic pin is driven by 0,1, or X
 - Acts as E2L when logic pin is undriven (Z)
L2E_1_ss   supply sensitive version of L2E_1 module


GENERAL INFORMATION:
================================
The parameters used for each of the rules files are defined in the 
"ConnRules*.vams" files.  They are parameterized so that one set of 
parameters can be specified, then applied to the full, full_fast, and basic
rules definitions.  These files can be copied and edited as desired to
define rules that are appropriate for your specific application.

Note that the connect modules are defined with a timescale of 1ns/100ps.
If higher accuracy values are to be passed into the cells, the files
should be edited to specify the higher resolution.  The timescale of 1ns
is assumed in the models:  changing the units value will require an
update to the calculation of "txdig" in the complete models.

See the header information in each of the connection module files in this
directory for more specific comments on the operation of the modules and
their available parameters.  The rules files described here are only 
intended as examples of usage.  They provide some reasonable numbers for
voltage levels, impedances, and timing information, but are not intended
to define any particular process.

The following matrix indicates what parameters are available for each of
the connection modules.  The parameters in the modules are defined with
defaults computed from other parameters, so that unspecified parameters
will be given reasonable values.  See the module headers for specific
definitions of the defaults and descriptions of the parameters, and the
connection rules files for parameter values used for each set of rules.

PARAM  E2L    E2L_2  E2L_0  L2E    L2E_2  L2E_1  L2E_0  Bidir  Bidir_2 Bidir_0
-----  -----  -----  -----  -----  -----  -----  -----  -----  -----   -----
vsup   *1     *      *      *1     *      *1     *      *1     *       *
vhi                         *2     *      *2     *      *2     *       *
vlo                         *2     *      *2     *      *2     *       *
vthi   *2     *      *      *2     *                    *2     *       *
vtlo   *2     *      *      *2     *                    *2     *       *
vx                          *2     *                    *2     *
vz                          *2     *                    *2
vxz                                       *2                           *
tr     *      *      *      *      *      *      *      *      *       *
tf                          *      *                    *      *
tx                          *                           *      *
tz                          *                           *      *
txdel  *      *             *                           *      *
rlo                         *      *                    *      *
rhi                         *      *                    *      *
rx                          *      *                    *      *
rz                          *      *                    *      *
rout                                      *      *                     *
vtol   *2            *      *2     *                    *2     *       *
ttol   *             *      *                           *              *
ttol_c        *                                                *        
ttol_t                             *                           *        
-----  -----  -----  -----  -----  -----  -----  -----  -----  -----   -----

Notes:
  1 - "vsup" is not a parameter for supply sensitive connect modules.
  2 - For supply sensitive connect modules, all voltage parameters
      have been redefined to be fractional scale factors, ranging
      from 0.0 (maps to groundSensitivity voltage) through 1.0 (maps
      to supplySensitivity voltage).
