// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module PLL_160MHZ ( SIDDQ,IPLY_25u,DISABLE,IEXT_100u,CLK_25MHZ,
CLK_160MHZ,CP_ITEST_25u,VDD,IEXT_25u,VSS ); 

input   SIDDQ;
input   IPLY_25u;
input   DISABLE;
input   IEXT_100u;

input   CLK_25MHZ;
output   CLK_160MHZ;
output   CP_ITEST_25u;
input  
 VDD;
input   IEXT_25u;
input   VSS;

 
 
 
gpdk090_nmoscap2v #(.m(1 * 100), .l(12.87u), .w(14.365u)) (*
integer 
library_binding = "gpdk090";
integer passed_mfactor = "m";
 *)
C4 ( 
VSS, VDD, VSS, VSS );
 
or2_4x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I84 ( .Y( PD ), .B( SIDDQ ), .A( DISABLE ) );
 
PLL_ARST_DIG (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I32 ( .DUMP( DUMP ), .COMP( CMPOUT ), .VDD( VDD ), .REFCLK( 
\5MHz_CLK  ), .PD( PD ), .VSS( VSS ) );
 
PLL_ARST (*
integer library_binding = "ether";
 *)
I34 ( .COMP( CMPOUT ), 
.LFTAP( TAP ), .VDD( VDD ), .PD( PD ), .VSS( VSS ), .Ibias( IEXT_25u ) );
 
PLL_160MHZ_MDIV (*
integer library_binding = "ether";
integer 
cds_net_set[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer 
DVDD = "VDD";
 *)
I24 ( .CLKFB( FBCLK ), .CLK160( CLK_160MHZ ), .CLKVCO( 
net036 ), .VDD( VDD ), .VSS( VSS ) );
 
PLL_160MHZ_PDIV (*
integer library_binding = "ether";
integer 
cds_net_set[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer 
DVDD = "VDD";
 *)
I23 ( .DIV( \5MHz_CLK  ), .VDD( VDD ), .CLK( 
CLK_25MHZ ), .VSS( VSS ) );
 
PLL_VCO_320MHZ (*
integer library_binding = "ether";
 *)
I13 ( .IEXT_100u( 
IEXT_100u ), .VDD( VDD ), .PD( PD ), .VCO_CLK( net036 ), .VSS( VSS ), 
.Vcontrol( vCNTL ) );
 
PLL_PFD (*
integer library_binding = "ether";
integer cds_net_set[0:1]
 = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS = "VSS";
 *)

I11 ( .VDD( VDD ), .REFCLK( \5MHz_CLK  ), .UP( UP ), .PD( PD ), .VSS( 
VSS ), .DN( DN ), .FBCLK( FBCLK ) );
 
PLL_CP (*
integer library_binding = "ether";
 *)
I12 ( .IPLY_25u( 
IPLY_25u ), .CP_ITEST_25u( CP_ITEST_25u ), .VDD( VDD ), .UP( UP ), .OUT( 
vCNTL ), .PD( PD ), .DN( DN ), .VSS( VSS ) );
 
PLL_160MHZ_LF (*
integer library_binding = "ether";
 *)
I18 ( .DUMP( 
DUMP ), .TAP( TAP ), .LF( vCNTL ), .VSS( VSS ) );

endmodule
