// Verilog-AMS netlist generated by the AMS netlister, version 5.10.41.500.1.14.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module adc_decode ( adc_flash,adc_out,ph1,ph1b,adcflash,adc,FX_BIT,
BASEFX_DIS,adc_latch_clk ); 

output [2:0]  adc_flash;
output [5:0]  adc_out;
input   ph1;
input  
 ph1b;
input [5:0]  adcflash;
input [62:0]  adc;
input   FX_BIT;

input   BASEFX_DIS;
output   adc_latch_clk;

wire [0:2] net024;
wire [62:0] adc;
wire ph1b;
wire [2:0] adc_flash;
wire adc_latch_clk;
wire BASEFX_DIS;
wire ph1;
wire [5:0] adc_out;
wire [5:0] adcflash;
wire FX_BIT;
 
 
 
adcflash_latches (*
integer library_binding = "ether";
 *)
flash_lat
 ( .in( net024[0:2] ), .out( adc_flash[2:0] ), .CLK( ph1b ) );
 
adc_therm2bin (*
integer library_binding = "ether";
 *)
adc_t2b ( .THERM( 
adc[62:0] ), .BIN( adc_out[5:0] ), .CLK125( ph1b ) );
 
adcflash_therm2bin (*
integer library_binding = "ether";
 *)
flash_t2b
 ( .THERM( adcflash[5:0] ), .BIN( net024[0:2] ), .BASEFX_DIS( 
BASEFX_DIS ), .CLK125( ph1 ), .FX_BIT( FX_BIT ) );
 
INVX1 (*
integer library_binding = "gsclib090";
 *)
i_2122 ( .Y( 
adc_latch_clk ), .A( ph1b ) );

endmodule
