// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module adcflash_latches ( out,CLK,in ); 

output [2:0]  out;
input   CLK;
input [2:0]  in;

wire [2:0] in;
wire [2:0] out;
wire CLK;
 
 
 
DFFX1 (*
integer library_binding = "gsclib090";
 *)
out_reg_2 ( .QN( 
net7 ), .D( in[2] ), .CK( CLK ), .Q( out[2] ) );
DFFX1 (*
integer library_binding = "gsclib090";
 *)
out_reg_1 ( .QN( 
net11 ), .D( in[1] ), .CK( CLK ), .Q( out[1] ) );
DFFX1 (*
integer library_binding = "gsclib090";
 *)
out_reg_0 ( .QN( 
net15 ), .D( in[0] ), .CK( CLK ), .Q( out[0] ) );

endmodule
