//--------------------
// dac_6bit_ideal
//
// -  6 bit digital analog converter
//
// vd0..vd5:	data inputs [V,A]
// vout:	[V,A]
//
// INSTANCE parameters
//    vcm    = ADC input signal Common Mode
//    vswing = A to D input signal swingD
//    trf    = Rise/fall time
//

`include "constants.vams"
`include "disciplines.vams"

module lye_dac_6bits ( vout, vd0, vd1, vd2, vd3, vd4, vd5 );

output vout;
input vd5, vd4, vd3, vd2, vd1, vd0;

electrical vout;
logic vd5, vd4, vd3, vd2, vd1, vd0;

parameter real vref   = 0.4;		// Common Mode VOltage of ADC input
parameter real vswing = 0.200;		// ADC Input Signal Swing
parameter real tdel   = 0;
parameter real trf    = 100p ;

integer iscale;
real sign, vvout;

initial iscale = 0;
always @(vd5 or vd4 or vd3 or vd2 or vd1 or vd0) begin
	iscale  =  vd4*16 + vd3*8 + vd2*4 + vd1*2 + vd0;
        sign = vd5;
end

analog begin
        @(initial_step) vvout = 0;
	vvout = (sign > 0) ? (vref*iscale/32.0)-vref :(vref*iscale/31.0);
//	V(vout) <+ transition( vvout,0,trf,trf);
	V(vout) <+ slew( vvout,2.5e10);

end

endmodule
