// 'E2L_0.vams' - Verilog-AMS connection rules file.
// last revised: 10/22/02 (ronv)
//
// REVISION HISTORY:
// Created:  4/05/02 ronv
// Updated:  4/19/02 ronv - updated param names
// Updated:  6/26/02 ronv - updated comments
// Updated:  9/14/02 ronv - added tr for ttol reference, loosened default ttol
// Updated: 10/22/02 ronv - updated from @cross to @above format, limit vtol
//
//============================================================================
// E2L_0(Ain,Dout)
// - Simple two-level electrical to logic conversion.
//
// Digital output immediately follows analog input changes.  Default
// thresholds assume hysteresis (output goes high at 2/3, low at 1/3 of 
// supply voltage).  Hysteresis can be removed by setting vthi=vtlo.
//
// LIMITATIONS:
//  This is the simplest of electrical to logic conversions.  If the logic
//  needs to be aware of an input that enters the X region between the 
//  specified thresholds, use the E2L model.
//
//  For more information on which connect module to select, please refer to:
//    .../tools/affirma_ams/etc/connect_lib/README
//

// INCLUDE FILES:
`include "disciplines.vams"
`timescale 1ns / 100ps

//============================================================================
connectmodule E2L_0(Ain,Dout);
 input Ain; electrical Ain;     // analog input signal
 output Dout; \logic Dout;      // digital output signal
 
 parameter real vsup=1.8;       // supply voltage (defines default params)
 parameter real vthi=vsup/1.5;  // upper threshold for analog transition
 parameter real vtlo=vthi/2;    // lower threshold for analog transition
 parameter real vtol=vsup/100;  // threshold detect voltage tolerance
 parameter real tr=0.2n from (0:1m);  // risetime (for tolerance)
 parameter real ttol=tr/3;      // time tol of crossing
 reg Kout;                      // register to hold output

//============================================================================
 initial Kout = (V(Ain)>(vthi+vtlo)/2);       // get init state from analog 
 always @( above( V(Ain)-vthi, ttol, vtol ) )  Kout=1'b1;  // high threshold
 always @( above( vtlo-V(Ain), ttol, vtol ) )  Kout=1'b0;  // low threshold
 assign Dout = Kout;                                       // drive output 
endmodule
