//Revision 8
//NOTE
// Default template for spectreVerilog
// Note:
//      Please remember to replace Top Cell Library, Cell, and View
//      fields with the actual names used by your design.
//END_NOTE

config adc_sim;
design ether_sims.adc_sim:schematic;

const analog spectre, spice, schematic, cmos_sch, veriloga, ahdl;
const digital verilog, behavioral, functional, hdl, system, verilogNetlist, schematic, cmos_sch;
const \default  spectre, spice, verilog, behavioral, functional, hdl, system, verilogNetlist, schematic, cmos_sch, veriloga, ahdl;
liblist myLib;

viewlist $\default ;
stoplist spectre, spice, verilog, verilogNetlist;


cell ether_sims.nand2_2x_hv binding :behavioral;
cell ether_sims.clkbuf_8x_hv binding :schematic;
cell ether_sims.inv_2x_hv binding :behavioral;


endconfig
