// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module pi_lvshift ( phase_2p5v,phase_1p0v,AVDD_2p5V,DVDD,AGND ); 

input [21:0]  phase_2p5v;
output [21:0]  phase_1p0v;
input  
 AVDD_2p5V;
input   DVDD;
input   AGND;

 
 
level_shifter_2p5_1p0 (*
integer library_binding = "ether";
integer 
elaboration_binding = "I0[21:0]";
 *)
I0_21 ( .IN( phase_2p5v[21] ), .VDD_1p0( 
DVDD ), .VDD_2p5( AVDD_2p5V ), .OUT( phase_1p0v[21] ), .VSS( AGND ) ),
  I0_20 ( .IN( phase_2p5v[20] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[20] ), .VSS( AGND ) ),
  I0_19 ( .IN( phase_2p5v[19] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[19] ), .VSS( AGND ) ),
  I0_18 ( .IN( phase_2p5v[18] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[18] ), .VSS( AGND ) ),
  I0_17 ( .IN( phase_2p5v[17] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[17] ), .VSS( AGND ) ),
  I0_16 ( .IN( phase_2p5v[16] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[16] ), .VSS( AGND ) ),
  I0_15 ( .IN( phase_2p5v[15] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[15] ), .VSS( AGND ) ),
  I0_14 ( .IN( phase_2p5v[14] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[14] ), .VSS( AGND ) ),
  I0_13 ( .IN( phase_2p5v[13] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[13] ), .VSS( AGND ) ),
  I0_12 ( .IN( phase_2p5v[12] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[12] ), .VSS( AGND ) ),
  I0_11 ( .IN( phase_2p5v[11] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[11] ), .VSS( AGND ) ),
  I0_10 ( .IN( phase_2p5v[10] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[10] ), .VSS( AGND ) ),
  I0_9 ( .IN( phase_2p5v[9] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[9] ), .VSS( AGND ) ),
  I0_8 ( .IN( phase_2p5v[8] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[8] ), .VSS( AGND ) ),
  I0_7 ( .IN( phase_2p5v[7] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[7] ), .VSS( AGND ) ),
  I0_6 ( .IN( phase_2p5v[6] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[6] ), .VSS( AGND ) ),
  I0_5 ( .IN( phase_2p5v[5] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[5] ), .VSS( AGND ) ),
  I0_4 ( .IN( phase_2p5v[4] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[4] ), .VSS( AGND ) ),
  I0_3 ( .IN( phase_2p5v[3] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[3] ), .VSS( AGND ) ),
  I0_2 ( .IN( phase_2p5v[2] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[2] ), .VSS( AGND ) ),
  I0_1 ( .IN( phase_2p5v[1] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[1] ), .VSS( AGND ) ),
  I0_0 ( .IN( phase_2p5v[0] ), .VDD_1p0( DVDD ), .VDD_2p5( AVDD_2p5V ), 
.OUT( phase_1p0v[0] ), .VSS( AGND ) );

endmodule
