// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module TIELO ( .VDD(\VDD! ),Y,.VSS(\VSS! ) ); 

input  (*
integer inh_conn_prop_name = "VDD";
integer 
inh_conn_def_value = "cds_globals.\\VDD! ";
 *)
 \VDD! ;
output   Y;

input  (*
integer inh_conn_prop_name = "VSS";
integer 
inh_conn_def_value = "cds_globals.\\VSS! ";
 *)
 \VSS! ;

wire (*
integer inh_conn_prop_name = "VDD";
integer inh_conn_def_value
 = "cds_globals.\\VDD! ";
 *)
\VDD! ;
wire net25;
wire Y;
wire (*
integer inh_conn_prop_name = "VSS";
integer inh_conn_def_value
 = "cds_globals.\\VSS! ";
 *)
\VSS! ;
 
 
gpdk090_pmos1v #(.ps(1.04u), .m(1 * 1), .as(69.6f), .l(1E-07), .pd(1.04u),
 .ad(69.6f), .w(120n)) (*
integer library_binding = "gpdk090";

integer passed_mfactor = "m";
 *)
mp0 ( net25, net25, \VDD! , \VDD!  );
 
gpdk090_nmos1v #(.ps(1.04u), .m(1 * 1), .as(69.6f), .l(1E-07), .pd(1.04u),
 .ad(69.6f), .w(120n)) (*
integer library_binding = "gpdk090";

integer passed_mfactor = "m";
 *)
mn0 ( Y, net25, \VSS! , \VSS!  );

endmodule
