// 'ConnRules_5V.vams' - Verilog-AMS 5 volt connection rules file.
// last revised:  01/25/06 (jhou)
//
// REVISION HISTORY:
// Created:  10/22/02 (ronv)
// Updated:  01/25/06 (jhou) - Added ConnRules_5V_full_fast.
// Updated:  09/08/06 (jlz)  - Added include disciplines.vams so electrical
//                             discipline is available for AMSVF flow.

// This line is added to make sure that all connect rules are 
// defined by default When ncverilog is run with
// +define+CDS_SELECT_CRS, the connect rules are defined
// selectively based on other +define settings that are sent to 
// ncverilog

`ifndef CDS_SELECT_CRS
`define CONNRULES_5V_FULL_FAST
`define CONNRULES_5V_FULL
`define CONNRULES_5V_MID
`define CONNRULES_5V_BASIC
`endif

// This file is a template for definition of rules for a particular 
// logic family.  Values for some typical parameters are defined here,
// then used in the three sets of connections rules below.
// See the "README.txt" file for a more complete usage description.

`include "disciplines.vams"

`define Vsup  5.0
`define Vthi  3.5
`define Vtlo  1.5
`define Tr    1n
`define Rlo   200
`define Rhi   200
`define Rx    40
`define Rz    10M
`define Vdelta      `Vsup/64
`define Vdelta_tol  `Vdelta/4
`define Tr_delta    `Tr/20

`ifdef CONNRULES_5V_FULL_FAST
connectrules ConnRules_5V_full_fast;
  connect L2E_2 #(
      .vsup(`Vsup),
      .tr(`Tr), .tf(`Tr),
      .rlo(`Rlo), .rhi(`Rhi), .rx(`Rx), .rz(`Rz) );
  connect E2L_2 #(
      .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Tr) );
  connect Bidir_2 #(
      .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo),
      .tr(`Tr), .tf(`Tr),
      .rlo(`Rlo), .rhi(`Rhi), .rx(`Rx), .rz(`Rz) );
  connect E2R #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta));
  connect R2E #(.vdelta(`Vdelta), .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo));
  connect ER_bidir #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta),
        .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo), .rz(`Rz));
endconnectrules
`endif

`ifdef CONNRULES_5V_FULL
connectrules ConnRules_5V_full;
  connect L2E #(
      .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo),
      .tr(`Tr), .tf(`Tr), .tx(`Tr), .tz(`Tr),
      .rlo(`Rlo), .rhi(`Rhi), .rx(`Rx), .rz(`Rz) );
  connect E2L #(
      .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Tr) );
  connect Bidir #(
      .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo),
      .tr(`Tr), .tf(`Tr), .tx(`Tr), .tz(`Tr),
      .rlo(`Rlo), .rhi(`Rhi), .rx(`Rx), .rz(`Rz) );
  connect E2R #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta));
  connect R2E #(.vdelta(`Vdelta), .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo));
  connect ER_bidir #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta),
        .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo), .rz(`Rz));
endconnectrules
`endif

`ifdef CONNRULES_5V_MID
connectrules ConnRules_5V_mid;
  connect E2L #( .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Tr) );
  connect L2E_1 #( .vsup(`Vsup), .tr(`Tr), .rout(`Rlo) );
  connect Bidir_0 #( .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo),
                   .tr(`Tr), .rout(`Rlo) );
  connect E2R #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta));
  connect R2E #(.vdelta(`Vdelta), .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo));
  connect ER_bidir #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta),
        .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo), .rz(`Rz));
endconnectrules
`endif

`ifdef CONNRULES_5V_BASIC
connectrules ConnRules_5V_basic;
  connect E2L_0 #( .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo), .tr(`Tr) );
  connect L2E_0 #( .vsup(`Vsup), .tr(`Tr), .rout(`Rlo) );
  connect Bidir_0 #( .vsup(`Vsup), .vthi(`Vthi), .vtlo(`Vtlo),
                   .tr(`Tr), .rout(`Rlo) );
  connect E2R #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta));
  connect R2E #(.vdelta(`Vdelta), .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo));
  connect ER_bidir #(.vdelta(`Vdelta), .vtol(`Vdelta_tol), .ttol(`Tr_delta),
        .tr(`Tr_delta), .tf(`Tr_delta), .rout(`Rlo), .rz(`Rz));
endconnectrules
`endif