// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module tenbt_rec_squelch_4in_mux ( MR_SQUELCH_DISB,RX10_PRESENT,gnd,
sq_10_low,sq_10_high,vdd,sq_11_low,sq_01_high,sq_off,squelch_ref_out,
sq_00_low,squelch_sel,sq_01_low,sq_00_high,sq_11_high ); 

input   MR_SQUELCH_DISB;
input   RX10_PRESENT;
input   gnd;
input  
 sq_10_low;
input   sq_10_high;
input   vdd;
input   sq_11_low;

input   sq_01_high;
input   sq_off;
output   squelch_ref_out;
input  
 sq_00_low;
input [1:0]  squelch_sel;
input   sq_01_low;
input  
 sq_00_high;
input   sq_11_high;

 
 
 
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I10
 ( .in0( net72 ), .in1( sq_off ), .gnd( gnd ), .vdd( vdd ), .out( 
squelch_ref_out ), .sel( MR_SQUELCH_DISB ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I6 ( 
.in0( net55 ), .in1( net47 ), .gnd( gnd ), .vdd( vdd ), .out( net72 ), 
.sel( RX10_PRESENT ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I5 ( 
.in0( sq_00_low ), .in1( sq_01_low ), .gnd( gnd ), .vdd( vdd ), .out( 
net37 ), .sel( squelch_sel[0] ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I4 ( 
.in0( sq_10_low ), .in1( sq_11_low ), .gnd( gnd ), .vdd( vdd ), .out( 
net31 ), .sel( squelch_sel[0] ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I3 ( 
.in0( net37 ), .in1( net31 ), .gnd( gnd ), .vdd( vdd ), .out( net47 ), 
.sel( squelch_sel[1] ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I2 ( 
.in0( net25 ), .in1( net19 ), .gnd( gnd ), .vdd( vdd ), .out( net55 ), 
.sel( squelch_sel[1] ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I1 ( 
.in0( sq_10_high ), .in1( sq_11_high ), .gnd( gnd ), .vdd( vdd ), .out( 
net19 ), .sel( squelch_sel[0] ) );
tenbt_rec_sq_cmref_mux (*
integer library_binding = "ether";
 *)
I0 ( 
.in0( sq_00_high ), .in1( sq_01_high ), .gnd( gnd ), .vdd( vdd ), .out( 
net25 ), .sel( squelch_sel[0] ) );

endmodule
