# Table File  : '/project/tsmc13lv98/sims/aptivia/workarea/pll/divider/dcmlib/PLL_250MHZ_MDIV/verilogams/PLL_250MHZ_MDIV_rise_CLKVCO_CLKFB_t2.vat'
# Result File : 'results/schroeder_sims/PLL_250MHZ_MDIVDCM/configDCM/results/_o_div10_VerilogA_timing_sweep-_o_div10_timing.res'
# Created on  : 'Wed Jan  7 2004 at 18:05:26'

# dcm_global_VDD_value
# 	rise_CLKVCO_CLKFB:t2
2	8.09527e-10 	# keys='2 '
2.65	6.51868e-10 	# keys='2.65 '
