//Revision 57
//NOTE
// Default template for spectreVerilog
// Note:
//      Please remember to replace Top Cell Library, Cell, and View
//      fields with the actual names used by your design.
//END_NOTE

config adc_top_ahdl_vs_sch_sim;
design ether_sims.adc_top_ahdl_vs_sch_sim:schematic;

const analog spectre, spice, schematic, cmos_sch, veriloga, ahdl;
const digital verilog, behavioral, functional, hdl, system, verilogNetlist, schematic, cmos_sch;
const \default  spectre, spice, verilog, behavioral, functional, hdl, system, verilogNetlist, schematic, cmos_sch, veriloga, ahdl;
liblist ether_sims;

viewlist spectre, schematic, cmos_sch, ahdl, verilog, behavioral;
stoplist spectre, verilog;


cell ether_sims.adc_top binding :schematic;
inst (ether_sims.test_adc_top_SIM:schematic).ADC_TOP binding :ahdl;
inst (ether_sims.test_adc_top_SIM:schematic).I67 binding :schematic;
inst (ether_sims.adc_top_ahdl_vs_sch_SIM:schematic).ADC_TOP binding :ahdl;
inst (ether_sims.adc_top_ahdl_vs_sch_SIM:schematic).I67 binding :behavioral;

inst (shawnee_ms.adc_therm2bin_SIM:schematic).I21 binding :behavioral;
cell shawnee_ms.jrb_adc_therm2bin binding :behavioral;
inst (shawnee_ms.adc_comparator_actr:schematic).I10 binding :cmos_sch;
inst (shawnee_ms.adc_comparator_actr:schematic).I11 binding :cmos_sch;
inst (shawnee_ms.adc_comparator_actr:schematic).I14 binding :cmos_sch;
inst (shawnee_ms.adc_comparator_actr:schematic).I15 binding :cmos_sch;
inst (shawnee_ms.adc_IREF_bias:schematic).I2 binding :cmos_sch;
inst (shawnee_ms.adc_top:schematic).I18 binding :cmos_sch;
inst (shawnee_ms.adc_top:schematic).I22 binding :cmos_sch;


endconfig
