// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module blw_dac_cell_new_8_1 ( pos,avdd,up,neg,vbiasp,siddq,agnd,down ); 

output   pos;
input   avdd;
input [7:0]  up;
output   neg;
input  
 vbiasp;
input   siddq;
input   agnd;
input [7:0]  down;

 
 
 
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I9 ( .avdd( 
avdd ), .pos( pos ), .up( up[2] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[2] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I8 ( .avdd( 
avdd ), .pos( pos ), .up( up[0] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[0] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I7 ( .avdd( 
avdd ), .pos( pos ), .up( up[1] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[1] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I3 ( .avdd( 
avdd ), .pos( pos ), .up( up[4] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[4] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I4 ( .avdd( 
avdd ), .pos( pos ), .up( up[5] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[5] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I2 ( .avdd( 
avdd ), .pos( pos ), .up( up[6] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[6] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I6 ( .avdd( 
avdd ), .pos( pos ), .up( up[3] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[3] ) );
blw_dac_cell_new_1 (*
integer library_binding = "ether";
 *)
I0 ( .avdd( 
avdd ), .pos( pos ), .up( up[7] ), .neg( neg ), .vbiasp( vbiasp ), .agnd( 
agnd ), .siddq( siddq ), .down( down[7] ) );

endmodule
