//Revision 73
config pll_250MHz_start_sim;
design ether_sims.pll_250MHz_start_sim:schematic;
liblist ether_sims, ether, basic, analogLib, gpdk090, gsclib090;

viewlist spectre, ahdl, schematic, cmos_sch, behavioral, verilog, av_extracted, av_extractedRC, symbol;
stoplist spectre;


inst (shawnee_ms.kf__sim_PLL_160MHZ_start:schematic).I3 binding :av_extractedRC;
inst (shawnee_ms.kf__sim_VCO_320MHz:schematic).I0 binding :av_extractedRC;
inst (shawnee_ms.kf__sim_PLL_250MHZ_start:schematic).I3 binding :av_extractedRC;

cell ether_sims.PLL_250MHZ binding :schematic;

cell ether.PLL_250MHZ binding :ahdl;
cell ether.PLL_250MHZ_MDIV binding :veriloga;
cell ether.PLL_VCO_250MHZ binding :veriloga;
cell ether.PLL_PFD binding :veriloga;
cell ether.PLL_CP binding :veriloga;


endconfig
