# Table File  : '/usr1/volden/etherPhy90/design/custom_cdba/VSdE_Workspace/VCME_PLL/dcmlib/PLL_250MHZ_MDIV/veriloga/PLL_250MHZ_MDIV_rise_CLKVCO_CLKFB_t2.vat'
# Result File : 'results/ether/PLL_250MHZ_MDIVDCM/configDCM/results/divider_VerilogA_timing_sweep-divider_timing.res'
# Created on  : 'Mon Dec 13 2004 at 15:26:53'
# Created by  : 'volden'

# dcm_global_VDD_value
# 	rise_CLKVCO_CLKFB:t2
2.4	8.45477e-10 	# keys='2.4'
2.5	8.04983e-10 	# keys='2.5'
2.6	7.68925e-10 	# keys='2.6'
