// Verilog-AMS cds_globals module for top-level cell:
//    ether_sims/top_sim.
// Generated by ADE.
// Cadence Design Systems, Inc.

// This is an autoGenerated file, any changes done to this file may get lost.

`include "disciplines.vams"

module cds_globals;

// Global Signals
   electrical \gnd! ;
   ground \gnd! ;
   wire \VDD! ;
   wire \VSS! ;
   wire \VDD_2p5! ;
   wire \VDD_1p0! ;
   wire \vss! ;
   wire \vdda! ;

// Design Variables
   dynamicparam real vdd_nom = 2.5;
   dynamicparam real vdd_1p0 = 1.0;
   dynamicparam real R = 100;
   dynamicparam real fvco = 2.5E+09;
   dynamicparam real freg = 416.7M;

endmodule
