// L2E_2.vams - Efficient logic-to-electrical connection module
// last revised:  04/18/06, jhou
//
// REVISION HISTORY:
// Created:  1/15/04 jhou
// Updated:  1/25/06 jhou - changed default tr to 0.2n
//           4/18/06 jhou - map digital X/Z to analog 0 by default
//                          in the full fast connect modules

/****************************************************************************
Description:

This logic-to-electrical connect module, L2E_2, is designed for better
simulation performance while having full support of unidirectional 4-level
(0, 1, X, and Z) logic to electrical value conversion. It has
the following different properties compared to connectmodule L2E:

1, For digital side driver-receiver segregation, L2E_2 performs a direct
   mapping from ordinary module drivers to ordinary module receivers
   without considering analog loading effect feedback, since it is
   unidirectional at the digital to analog boundary.
   On connections where analog loading effects need to be considered
   in the digital reciver side, the ports in ordinary modules need to be
   declared as inout so that Bidir_2 modules are used for the same.

2, Analog voltages of vx/vz, mapped from digital X/Z, are defaulted to
   vlo (which is 0 by default) with output impedance rx/rz.
   When the digital input changes from any value to Z at time > 0,
   the analog output voltage does not change but only the output
   impedance changes to rz (which is high impedance by default).
   In contrast, L2E maps digital Z/X to analog vsup/2 by default, which
   is a worst case analysis but does not cover all worst cases.

3, The output resistance upon digital X, rx, is default to 10 times the
   sum of output-low and output-high resistances, since the output
   resistance of a gate during transition is usually higher.

4, When digital input changes, both analog output voltage and resistance
   transition linearly. This usually improves the convergence of
   simulation.

5, A 10% of rise/fall time tolerance is added on transition filters for
   better performance, but the time tolerance is applied only 
   when strictly following the rise/fall time would significantly
   reduce the simulation speed.

****************************************************************************/

`include "disciplines.vams"
`timescale 1ns / 100ps

connectmodule L2E_2(Din,Aout);
 input Din; \logic Din;         // digital input signal
 output Aout; electrical Aout;  // analog output signal
 
 parameter real vsup=1.8          from (0:inf);      // nominal supply voltage
 parameter real vlo=0             from (-inf:vsup);  // logic low voltage
 parameter real vhi=vsup          from (vlo:vsup];   // logic high voltage
 parameter real vthi=vsup/1.5     from (vlo:vsup];   // upper threshold
 parameter real vtlo=vsup/3       from (vlo:vsup];   // lower threshold
 parameter real vx=vlo            from [vlo:vhi];    // X output voltage
 parameter real vz=vx             from [vlo:vhi];    // Z output voltage
 parameter real tr=0.2n           from (0:inf);  // risetime of analog output
 parameter real tf=tr             from (0:inf);  // falltime of analog output
 parameter real ttol_t=(tr+tf)/20 from (0:inf);  // time tol of transition
 parameter real tdelay=0          from [0:inf);  // delay time of analog output
 parameter real rhi=200           from (0:inf);      // output resistance
 parameter real rlo=rhi           from (0:inf);      // output resistance
 parameter real rz=10M            from (0:inf);      // output resistance
 parameter real rx=10*(rlo+rhi)   from (0:inf);      // output resistance

 real Vstate,Rout;              // output voltage & resistance states
 real rout;                     // analog output resistance
 
 assign Din = Din;              // direct driver-receiver propagation
 initial begin
    Vstate=vz; Rout=rz;         // initially map digital default to vz/rz
 end
 always begin
   case(Din)
     1'b0:  begin  Vstate=vlo; Rout=rlo;    end
     1'b1:  begin  Vstate=vhi; Rout=rhi;    end
     1'bz:  begin  Rout=rz;  end
     default:  begin Vstate=vx; Rout=rx;  end
   endcase
   @(Din); 
 end
 analog begin
  rout = transition(Rout,tdelay,tr,tf,ttol_t);     // rout shifts linearly also;
  @(initial_step) rout = rz;                  //Initially with no digital input;
  I(Aout) <+ (V(Aout)-transition(Vstate,tdelay,tr,tf,ttol_t))/rout; 
 end
endmodule
