// 'L2E_0.vams' - Verilog-AMS connection rules file.
// last revised:  10/22/02 (ronv)
//
// REVISION HISTORY:
// Created:  4/05/02 ronv
// Updated:  4/19/02 ronv - ignore X&Z rather than map to zero; update params
// Updated:  6/26/02 ronv - updated comments
// Updated:  8/30/02 ronv - removed optional output cap
// Updated: 10/22/02 ronv - updated comments
//
//============================================================================
// L2E_0(Din,Aout)
// - Simple two-level logic to electrical conversion.
//
// Output changes to high or low; X or Z on logic side is ignored.
// No analog loading effects are implemented here: it's just a logic to
// electrical unidirectional conversion.
//
// LIMITATIONS:
//  This is only the most basic of D to A conversion formats.  If there are
//  any significant X or Z states that can appear at an interface, use the
//  L2E_1 model.  If there are any logic contensions that must be worked 
//  out on the analog side of the interface, a complete connect module
//  that includes digital feedback (L2E) should be used.
//
//  For more information on which connect module to select, please refer to:
//    .../tools/affirma_ams/etc/connect_lib/README
//

// INCLUDE FILES:
`include "disciplines.vams"
`timescale 1ns / 100ps

//============================================================================
connectmodule L2E_0(Din,Aout);
 input Din; \logic Din;         // digital input signal
 output Aout; electrical Aout;  // analog output signal
 
 parameter real vsup=1.8;       // supply voltage (defines default params)
 parameter real vhi=vsup;       // high output level
 parameter real vlo=0;          // low output level
 parameter real tr=0.2n;        // risetime of analog output
 parameter real rout=200;       // output resistance

 reg Dreg;                      // register for logic writeback
 real Vstate,Vout;              // output voltage (state & with transition)
 real Arg;			// argument for derivative for output cap
 
//============================================================================
 assign Din = Dreg;             // assign digital value to input pin. 
 initial begin
   Dreg = Din;                  // initial logic writeback
   Vstate = (Din===1)? vhi:vlo; // set initial output voltage
 end
 always @Din  begin
   Dreg = Din;                         // logic writeback follows level.
   if (Din===0 || Din===1)             // if change to high or low,
        Vstate = Din? vhi:vlo;         // update analog output voltage.
 end
 analog begin
   Vout = transition(Vstate,0,tr,tr);  // add risetimes to Vstate
   I(Aout) <+ (V(Aout)-Vout)/rout;     // drive output with resistance
 end
endmodule
