// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module PLL_160MHZ_PDIV ( DIV,CLK,VDD,VSS ); 

output   DIV;
input   CLK;
input   VDD;
input   VSS;

wire [2:0] qb;
wire [1:0] q;
wire [2:0] d;
 
 
nor2_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I2 ( .Y( d[2] ), .B( qb[0] ), .A( qb[1] ) );
 
xor2_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I1 ( .Y( d[0] ), .B( q[0] ), .A( qb[2] ) );
xor2_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS
 = "VSS";
 *)
I5 ( .Y( d[1] ), .B( q[1] ), .A( q[0] ) );
 
clkbuf_4x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS
 = "VSS";
 *)
I6 ( .Y( clock ), .A( CLK ) );
clkbuf_4x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I24 ( .Y( DIV ), .A( net071 ) );
 
dff_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I4 ( .QN( qb[2] ), .D( d[2] ), .CK( clock ), .Q( net071 ) );
dff_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I3 ( .QN( qb[1] ), .D( d[1] ), .CK( clock ), .Q( q[1] ) );
dff_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS
 = "VSS";
 *)
I0 ( .QN( qb[0] ), .D( d[0] ), .CK( clock ), .Q( q[0] ) );

endmodule
