// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module dly1_1x_hv ( Y,A ); 

output   Y;
input   A;

wire (*
integer inh_conn_prop_name = "DVDD";
integer 
inh_conn_def_value = "cds_globals.\\VDD! ";
 *)
\VDD! ;
wire (*
integer inh_conn_prop_name = "DVSS";
integer 
inh_conn_def_value = "cds_globals.\\VSS! ";
 *)
\VSS! ;
 
 
 
gpdk090_pmos2v #(.ps(4u), .m(1 * 1), .as(840f), .l(280.0n), .pd(4u), .ad(840f),
 .w(1.4u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM3 ( Y, net35, \VDD! , \VDD!  );
gpdk090_pmos2v #(.ps(2.8u), .m(1 * 1), .as(480f), .l(460.0n), .pd(2.8u),
 .ad(480f), .w(800n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM2 ( net35, net39, \VDD! , \VDD!  );
gpdk090_pmos2v #(.ps(2.8u), .m(1 * 1), .as(460f), .l(460.0n), .pd(2.8u),
 .ad(460f), .w(500n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM1 ( net39, net43, \VDD! , \VDD!  );
gpdk090_pmos2v #(.ps(2.4u), .m(1 * 1), .as(360f), .l(280.0n), .pd(2.4u),
 .ad(360f), .w(600n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM0 ( net43, A, \VDD! , \VDD!  );
 
gpdk090_nmos2v #(.ps(2.8u), .m(1 * 1), .as(440f), .l(280.0n), .pd(2.8u),
 .ad(440f), .w(400n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
NM0 ( net43, A, \VSS! , \VSS!  );
gpdk090_nmos2v #(.ps(2.8u), .m(1 * 1), .as(440f), .l(460.0n), .pd(2.8u),
 .ad(440f), .w(400n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
NM2 ( net35, net39, \VSS! , \VSS!  );
gpdk090_nmos2v #(.ps(2.8u), .m(1 * 1), .as(472f), .l(280.0n), .pd(2.8u),
 .ad(472f), .w(560n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
NM3 ( Y, net35, \VSS! , \VSS!  );
gpdk090_nmos2v #(.ps(2.8u), .m(1 * 1), .as(440f), .l(460.0n), .pd(2.8u),
 .ad(440f), .w(400n)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
NM1 ( net39, net43, \VSS! , \VSS!  );

endmodule
