// Verilog-AMS cds_globals module for top-level cell:
//      VFS_AMS_PHY180_sims/amsultra_test.
// Generated by AMS.
// Cadence Design Systems, Inc.

`include "disciplines.vams"

module cds_globals;

// Global Signals
    wire \VDD1! ;
    wire \VSS! ;
    wire \GND! ;
    electrical \gnd! ;
    ground \gnd! ;
    wire \VDD! ;

endmodule
