// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module blw_dac ( BASE100_DIS,AEQ_DIS,IN,INP,SIDDQ,AVDD_2p5V,DGND,DVDD,
I_RPOLY_100_1,OUTP,OUTM,AGND,I_RPOLY_100_2,INM,ADC_TEST ); 

input   BASE100_DIS;
input   AEQ_DIS;
input [6:0]  IN;
input   INP;

input   SIDDQ;
input   AVDD_2p5V;
input   DGND;
input   DVDD;
input  
 I_RPOLY_100_1;
output   OUTP;
output   OUTM;
input   AGND;
input  
 I_RPOLY_100_2;
input   INM;
input   ADC_TEST;

wire [62:0] up_1v;
wire [62:0] down_1v;
wire [62:0] up;
wire [62:0] down;
 
parameter td=0;
parameter res_poly_scale=0;
parameter trf=1E-10;
 
 
 
gpdk090_resnsppoly #(.w(2u), .r(8.15545K), .l(40.7829u)) (*
integer 
library_binding = "gpdk090";
 *)
R33 ( Icm_200uA, AGND, AGND );
 
gpdk090_nmoscap2v #(.m(1 * 9), .l(12.87u), .w(12.82u)) (*
integer 
library_binding = "gpdk090";
integer passed_mfactor = "m";
integer 
elaboration_binding = "C0[8:0]";
 *)
C0_8 ( AGND, AVDD_2p5V, AGND, 
AGND ),
  C0_7 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_6 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_5 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_4 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_3 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_2 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_1 ( AGND, AVDD_2p5V, AGND, AGND ),
  C0_0 ( AGND, AVDD_2p5V, AGND, AGND );
 
gpdk090_pmos2v #(.ps(101.2u), .m(1 * 1), .as(30p), .l(300n), .pd(101.2u),
 .ad(30p), .w(50u)) (*
integer library_binding = "gpdk090";
integer 
passed_mfactor = "m";
 *)
PM4 ( OUTM, net446, OUTP, AVDD_2p5V );
 
blw_dac_mirror (*
integer library_binding = "ether";
 *)
I54 ( .dac_I_out( 
OUTM ), .dac_I_in( dac_outn ), .AGND( AGND ) );
blw_dac_mirror (*
integer library_binding = "ether";
 *)
I53 ( .dac_I_out( 
OUTP ), .dac_I_in( dac_outp ), .AGND( AGND ) );
 
blw_dac_vbias_dac (*
integer library_binding = "ether";
 *)
I52 ( .AVDD_2p5V( 
AVDD_2p5V ), .vbiasp_bit( vbiasp_bit ), .ibiasp_20u( net0265 ) );
 
blw_dac_typIsource_1p26mA (*
integer library_binding = "ether";
 *)

I51 ( .vbiasp_output( vbiasp_output ), .SIDDQb( SIDDQb ), .ibiaspc_40u( 
net0196 ), .AVDD_2p5V( AVDD_2p5V ), .ibiasp_40u( net0197 ), .Icm_200uA( 
Icm_200uA ), .Isource1_tt1p26mA( OUTP ), .Isource2_tt1p26mA( OUTM ), .vbiaspc_output( 
vbiaspc_output ) );
 
inv_4x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "AVDD_2p5V";
integer DVSS
 = "AGND";
 *)
I49 ( .Y( SIDDQb ), .A( SIDDQ ) );
 
inv_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "AVDD_2p5V";
integer DVSS
 = "AGND";
 *)
I48 ( .Y( net441 ), .A( ADC_TEST ) );
 
nand3_2x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "AVDD_2p5V";
integer DVSS
 = "AGND";
 *)
I46 ( .C( SIDDQ ), .Y( net446 ), .B( AEQ_DIS ), .A( 
net441 ) );
 
blw_dac_lvshift (*
integer library_binding = "ether";
 *)
I47 ( .up_1v( 
up_1v[62:0] ), .AVDD_2p5V( AVDD_2p5V ), .DVDD( DVDD ), .down_1v( 
down_1v[62:0] ), .up_2p5v( up[62:0] ), .AGND( AGND ), .down_2p5v( 
down[62:0] ) );
 
blw_dac_ixf_cmf_v2 (*
integer library_binding = "ether";
 *)
I33 ( .Vref( 
Icm_200uA ), .AVDD_2p5V( AVDD_2p5V ), .Vbiasp( vbiasp_output ), .Vbiaspc( 
vbiaspc_output ), .Vbiasn( vbiasn_bit ), .vcm( vcm ), .Vcm_sense( vcm ), 
.siddq( SIDDQ ), .Vbiasnc( vbiasnc_bit ), .Ixf_m( OUTM ), .AGND( AGND ), 
.Ixf_p( OUTP ) );
 
blw_dac_in_res_v2 (*
integer library_binding = "ether";
 *)
I28 ( .INP( 
INP ), .OUTP( OUTP ), .Vcm( vcm ), .OUTM( OUTM ), .AGND( AGND ), .INM( 
INM ) );
 
blw_dac_cell_new_8_8 #(.d2a_tr(".2n"), .ieIO("output"), .d2a_tf(".2n"),
 .d2a_vh("1.8")) (*
integer library_binding = "ether";
 *)
I2 ( .pos( 
dac_outp ), .avdd( AVDD_2p5V ), .up( up[62:0] ), .neg( dac_outn ), .vbiasp( 
vbiasp_bit ), .siddq( SIDDQ ), .agnd( AGND ), .down( down[62:0] ) );
 
blw_dac_new_bias (*
integer library_binding = "ether";
 *)
I0 ( .I_rpoly_100_2( 
I_RPOLY_100_2 ), .AVDD_2p5V( AVDD_2p5V ), .I_rpoly_100_1( 
I_RPOLY_100_1 ), .vbiasn_bit( vbiasn_bit ), .ibiasp_output( net0197 ), 
.ibiasp_bit( net0265 ), .siddq( SIDDQ ), .agnd( AGND ), .vbiasnc_bit( 
vbiasnc_bit ), .ibiaspc_output( net0196 ) );
 
blw_dac_bin2therm #(.d2a_tr(".2n"), .ieIO("output"), .a2d_v0("1"), .d2a_tf(".2n"),
 .a2d_v1("1.5"), .d2a_vh("1")) (*
integer library_binding = "ether";

integer cds_net_set[0:1] = { "VDD","VSS" };
integer VDD = "DVDD";

integer VSS = "DGND";
 *)
I30 ( .bin_in( IN[6:0] ), .up( up_1v[62:0] ), 
.reset( BASE100_DIS ), .down( down_1v[62:0] ) );
 
capacitor #(.c(1p)) (*
integer library_binding = "analogLib";
 *)
C5
 ( OUTM, AGND );
capacitor #(.c(1p)) (*
integer library_binding = "analogLib";
 *)
C4
 ( OUTP, AGND );

endmodule
