// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module pi ( PHASE_DOWN,phin,RESET,AVDD_2p5V,PHASE_UP,VDD,RCLK125,AGND,
VSS,RCLK125_TEST,ADC_TEST_MODE ); 

input   PHASE_DOWN;
input [10:0]  phin;
input   RESET;
input  
 AVDD_2p5V;
input   PHASE_UP;
input   VDD;
output   RCLK125;
input  
 AGND;
input   VSS;
input   RCLK125_TEST;
input   ADC_TEST_MODE;

wire [21:0] phase_2p5v;
wire [21:0] phase_1p0v;
 
 
pi_lvshift #(.a2d_v0("0.5"), .a2d_v1("0.8")) (*
integer 
library_binding = "ether";
 *)
I3 ( .phase_2p5v( phase_2p5v[21:0] ), .phase_1p0v( 
phase_1p0v[21:0] ), .AVDD_2p5V( AVDD_2p5V ), .DVDD( VDD ), .AGND( AGND ) );
 
pi_dig_phase #(.d2a_tr("100p"), .ieIO("input"), .a2d_v0("0.5"), .d2a_tf("100p"),
 .d2a_vh("1"), .a2d_tx("100p"), .a2d_v1("0.8")) (*
integer 
library_binding = "ether";
integer cds_net_set[0:1] = { "VDD","VSS"
 };
integer VDD = "VDD";
integer VSS = "VSS";
 *)
I1 ( .RESET( RESET ), 
.PHASE_UP( PHASE_UP ), .CLK250_TAPS( phase_1p0v[21:0] ), .RCLK125( 
RCLK125 ), .PHASE_DN( PHASE_DOWN ), .RCLK125_TEST( RCLK125_TEST ), .ADC_TEST_MODE( 
ADC_TEST_MODE ) );
 
PI_interp #(.d2a_tr("100p"), .ieIO("output"), .a2d_v0("0.5"), .d2a_tf("100p"),
 .a2d_v1("0.8"), .d2a_vh("2.5")) (*
integer library_binding
 = "ether";
integer cds_net_set[0:1] = { "DVDD","DVSS" };
integer DVDD
 = "VDD";
integer DVSS = "VSS";
 *)
I0 ( .IN( phin[10:0] ), .VDD( 
AVDD_2p5V ), .OUT( phase_2p5v[21:0] ), .VSS( AGND ) );

endmodule
