// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module adc_top ( TEST_INM,INP,SIDDQ,TEST_ENABLE,adc_flash,DVDD,
BASE100TX_DIS,I100_ext2,I100_ext1,adc_latch_clk,DVSS,VDD,I100_poly1,
adc_out,TEST_INP,INM,CLK,VSS,I100_poly2,BASEFX_DIS_1p0 ); 

input   TEST_INM;
input   INP;
input   SIDDQ;
input   TEST_ENABLE;

output [2:0]  adc_flash;
input   DVDD;
input   BASE100TX_DIS;
input  
 I100_ext2;
input   I100_ext1;
output   adc_latch_clk;
input   DVSS;

input   VDD;
input   I100_poly1;
output [5:0]  adc_out;
input  
 TEST_INP;
input   INM;
input   CLK;
input   VSS;
input   I100_poly2;

input   BASEFX_DIS_1p0;

wire [62:0] adc_2p5;
wire [5:0] flash_2p5;
wire [62:0] adc_1p0;
wire [5:0] flash_1p0;
 
parameter Tsamp_out=4E-10;
parameter Tck_latch=7E-10;
parameter VH=0.4;
parameter Tck_samp=7E-10;
parameter VL=-0.4;
 
 
gpdk090_nmoscap2v #(.m(16 * 16), .l(12.87u), .w(12.82u)) (*
integer 
library_binding = "gpdk090";
integer passed_mfactor = "m";
 *)
C0 ( 
VSS, VDD, VSS, VSS );
 
adc_lvlshft_1p0_to_2p5 #(.mag(0.5)) (*
integer library_binding
 = "ether";
 *)
I29 ( .CLK_1p0( CLK ), .BASE100TX_DIS_2p5( 
BASE100TX_DIS_2p5 ), .BASE100TX_DIS_1p0( BASE100TX_DIS ), .VDD_1p0( 
DVDD ), .BASEFX_DIS_2p5( BASEFX_DIS_2p5 ), .CLK_2p5( CLK_2p5 ), .VDD_2p5( 
VDD ), .VSS( VSS ), .BASEFX_DIS_1p0( BASEFX_DIS_1p0 ) );
 
adc_lvlshft_2p5_to_1p0 (*
integer library_binding = "ether";
 *)
I27
 ( .FX_BIT_2p5( FX_BIT_2p5 ), .adc_2p5( adc_2p5[62:0] ), .ph1b_2p5( 
ph1b_2p5 ), .vss( VSS ), .flash_2p5( flash_2p5[5:0] ), .adc_1p0( 
adc_1p0[62:0] ), .VDD_1p0( DVDD ), .ph1b_1p0( ph1b_1p0 ), .ph1_2p5( 
ph1_2p5 ), .FX_BIT_1p0( FX_BIT_1p0 ), .VDD_2p5( VDD ), .ph1_1p0( 
ph1_1p0 ), .flash_1p0( flash_1p0[5:0] ) );
 
or2_2x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVSS","DVDD" };
integer DVSS = "VSS";
integer DVDD
 = "VDD";
 *)
I26 ( .Y( POWEROFF ), .B( net85 ), .A( SIDDQ ) );
 
and2_1x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS
 = "VSS";
 *)
I25 ( .Y( net85 ), .B( BASEFX_DIS_2p5 ), .A( 
BASE100TX_DIS_2p5 ) );
 
adc_decode #(.ieIO("input"), .a2d_v0(".5"), .a2d_tx("100p"), .d2a_vh("2.5"),
 .a2d_v1(".8")) (*
integer library_binding = "ether";
integer 
cds_net_set[0:1] = { "VDD","VSS" };
integer VDD = "DVDD";
integer VSS
 = "DVSS";
 *)
ADC_DECODE ( .ph1b( ph1b_1p0 ), .adc( adc_1p0[62:0] ), 
.adc_flash( adc_flash[2:0] ), .adc_latch_clk( adc_latch_clk ), .BASEFX_DIS( 
BASEFX_DIS_1p0 ), .ph1( ph1_1p0 ), .adc_out( adc_out[5:0] ), .adcflash( 
flash_1p0[5:0] ), .FX_BIT( FX_BIT_1p0 ) );
 
adc_wo_decode (*
integer library_binding = "ether";
 *)
ADC_WO_DECODE
 ( .TEST_INM( TEST_INM ), .INP( INP ), .SIDDQ( POWEROFF ), .TEST_ENABLE( 
TEST_ENABLE ), .ph1b( ph1b_2p5 ), .I100_ext2( I100_ext2 ), .I100_ext1( 
I100_ext1 ), .adcflash_out( flash_2p5[5:0] ), .VDD( VDD ), .I100_poly1( 
I100_poly1 ), .BASEFX_DIS( BASEFX_DIS_2p5 ), .ph1( ph1_2p5 ), .adc_out( 
adc_2p5[62:0] ), .CLK( CLK_2p5 ), .INM( INM ), .TEST_INP( TEST_INP ), 
.FX_BIT( FX_BIT_2p5 ), .VSS( VSS ), .I100_poly2( I100_poly2 ) );

endmodule
