// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module clock_buffer ( IN,OUT ); 

input   IN;
output   OUT;

 
 
 
inv_16x_hv #(.d2a_tr(".2n"), .ieIO("input"), .a2d_v0("0.85"), .d2a_tf(".2n"),
 .d2a_vh("1.8"), .a2d_v1("0.95")) (*
integer library_binding
 = "ether";
 *)
I74 ( .Y( OUT ), .A( net15 ) );
 
inv_8x_hv #(.ieIO("input"), .d2a_tr(".2n"), .a2d_v0("0.85"), .d2a_tf(".2n"),
 .d2a_vh("1.8"), .a2d_v1("0.95")) (*
integer library_binding
 = "ether";
 *)
I73 ( .Y( net15 ), .A( net10 ) );
 
inv_3x_hv #(.ieIO("input")) (*
integer library_binding = "ether";
 *)

I72 ( .Y( net10 ), .A( net7 ) );
 
inv_1x_hv #(.ieIO("input"), .a2d_v0("0.85"), .a2d_v1("0.95")) (*

integer library_binding = "ether";
 *)
I71 ( .Y( net7 ), .A( IN ) );

endmodule
