// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module blw_dac_cell_new_8_8 ( avdd,pos,up,neg,vbiasp,agnd,siddq,down ); 

input   avdd;
output   pos;
input [62:0]  up;
output   neg;
input  
 vbiasp;
input   agnd;
input   siddq;
input [62:0]  down;

 
 
blw_dac_cell_new_7_1 (*
integer library_binding = "ether";
 *)
I8 ( .pos( 
pos ), .avdd( avdd ), .up( up[6:0] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[6:0] ) );
 
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I0 ( .pos( 
pos ), .avdd( avdd ), .up( up[62:55] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[62:55] ) );
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I6 ( .pos( 
pos ), .avdd( avdd ), .up( up[30:23] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[30:23] ) );
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I2 ( .pos( 
pos ), .avdd( avdd ), .up( up[54:47] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[54:47] ) );
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I4 ( .pos( 
pos ), .avdd( avdd ), .up( up[46:39] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[46:39] ) );
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I3 ( .pos( 
pos ), .avdd( avdd ), .up( up[38:31] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[38:31] ) );
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I7 ( .pos( 
pos ), .avdd( avdd ), .up( up[14:7] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[14:7] ) );
blw_dac_cell_new_8_1 (*
integer library_binding = "ether";
 *)
I9 ( .pos( 
pos ), .avdd( avdd ), .up( up[22:15] ), .neg( neg ), .vbiasp( vbiasp ), 
.siddq( siddq ), .agnd( agnd ), .down( down[22:15] ) );

endmodule
