// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module PI_interp ( IN,VDD,OUT,VSS ); 

input [10:0]  IN;
input   VDD;
output [21:0]  OUT;
input   VSS;

 
parameter td=0;
parameter tr=0;
parameter tf=0;
 
 
PI_interp_tap_cell (*
integer library_binding = "ether";
 *)
I23 ( .VDD( 
VDD ), .TAP( { net142,VSS } ), .OUT( net018 ), .VSS( VSS ) );
PI_interp_tap_cell (*
integer library_binding = "ether";
 *)
I25 ( .VDD( 
VDD ), .TAP( { VSS,net037 } ), .OUT( net013 ), .VSS( VSS ) );
PI_interp_tap_cell (*
integer library_binding = "ether";
 *)
I16 ( .VDD( 
VDD ), .TAP( { net127,net113 } ), .OUT( OUT[7] ), .VSS( VSS ) );
PI_interp_tap_cell (*
integer library_binding = "ether";
 *)
I15 ( .VDD( 
VDD ), .TAP( { net102,net108 } ), .OUT( OUT[15] ), .VSS( VSS ) );
 
PI_interp_block (*
integer library_binding = "ether";
 *)
I20 ( .IN( { IN[0],
IN[10:8] } ), .Tap( { net037,net102 } ), .VDD( VDD ), .OUT( { net011,
OUT[21:16] } ), .VSS( VSS ) );
PI_interp_block (*
integer library_binding = "ether";
 *)
I7 ( .IN( 
IN[3:0] ), .Tap( { net113,net142 } ), .VDD( VDD ), .OUT( OUT[6:0] ), .VSS( 
VSS ) );
PI_interp_block (*
integer library_binding = "ether";
 *)
I8 ( .IN( 
IN[7:4] ), .Tap( { net108,net127 } ), .VDD( VDD ), .OUT( OUT[14:8] ), 
.VSS( VSS ) );

endmodule
