// Verilog-AMS netlist generated by the AMS netlister, version ICOA5.2.51.500.7.
// Cadence Design Systems, Inc.

`include "disciplines.vams"
 
module trans_ld_100TX_current_mirror ( MLT3,vbias,neg_out,VDD,pos_out,
siddq,switch_vbias,VSS ); 

input [1:0]  MLT3;
input   vbias;
output   neg_out;
input   VDD;

output   pos_out;
input   siddq;
input   switch_vbias;
input   VSS;

 
 
 
clkbuf_4x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS
 = "VSS";
 *)
I56 ( .Y( b ), .A( MLT3[1] ) );
clkbuf_4x_hv (*
integer library_binding = "ether";
integer cds_net_set
[0:1] = { "DVDD","DVSS" };
integer DVDD = "VDD";
integer DVSS
 = "VSS";
 *)
I55 ( .Y( a ), .A( MLT3[0] ) );
 
trans_ld_100TX_cm_cell_bias_hv (*
integer library_binding = "ether";

 *)
I52 ( .vbias( vbias ), .neg_out( neg_out ), .pos_out( pos_out ), .VDD( 
VDD ), .siddq( siddq ), .switch_vbias( switch_vbias ), .VSS( VSS ) );
 
trans_ld_100TX_cm_cell_hv (*
integer library_binding = "ether";
 *)

I54 ( .a( a ), .vbias( vbias ), .b( b ), .neg_out( neg_out ), .VDD( 
VDD ), .pos_out( pos_out ), .siddq( siddq ), .switch_vbias( 
switch_vbias ), .VSS( VSS ) );
trans_ld_100TX_cm_cell_hv (*
integer library_binding = "ether";
 *)

I26 ( .a( a ), .vbias( vbias ), .b( b ), .neg_out( neg_out ), .VDD( 
VDD ), .pos_out( pos_out ), .siddq( siddq ), .switch_vbias( 
switch_vbias ), .VSS( VSS ) );
trans_ld_100TX_cm_cell_hv (*
integer library_binding = "ether";
 *)

I37 ( .a( a ), .vbias( vbias ), .b( b ), .neg_out( neg_out ), .VDD( 
VDD ), .pos_out( pos_out ), .siddq( siddq ), .switch_vbias( 
switch_vbias ), .VSS( VSS ) );
trans_ld_100TX_cm_cell_hv (*
integer library_binding = "ether";
 *)

I38 ( .a( a ), .vbias( vbias ), .b( b ), .neg_out( neg_out ), .VDD( 
VDD ), .pos_out( pos_out ), .siddq( siddq ), .switch_vbias( 
switch_vbias ), .VSS( VSS ) );
trans_ld_100TX_cm_cell_hv (*
integer library_binding = "ether";
 *)

I40 ( .a( a ), .vbias( vbias ), .b( b ), .neg_out( neg_out ), .VDD( 
VDD ), .pos_out( pos_out ), .siddq( siddq ), .switch_vbias( 
switch_vbias ), .VSS( VSS ) );

endmodule
