

module delaycell (inh_NmosB, inh_PmosB, inh_gnd, inn, inp, nbias, outn,
    outp, pbias1, pbias2, inh_vdd);

//port section 
   inout inh_NmosB;
   inout inh_PmosB;
   inout inh_gnd;
   input inn;
   input inp;
   input nbias;
   output outn;
   output outp;
   input pbias1;
   input pbias2;
   inout inh_vdd;
   electrical ground;

//end port section 


//Spice primitive instantiations
      electrical inh_NmosB;
      electrical inh_PmosB;
      electrical inh_gnd;
      electrical inn;
      electrical inp;
      electrical nbias;
      electrical outn;
      electrical outp;
      electrical pbias1;
      electrical pbias2;
      electrical inh_vdd;
   analog begin
      $spice_prim(".import vdd!");
      $spice_prim("M3 net17 inn outp inh_PmosB P  w=6.3u l=0.42u m=2");
      $spice_prim("+ ad='6.3u*0.84u' pd='6.3u+1.68u' ps='6.3u+1.68u'");
      $spice_prim("+ as='6.3u*0.84u'");
      $spice_prim("M2 net17 inp outn inh_PmosB P  w=6.3u l=0.42u m=2");
      $spice_prim("+ ad='6.3u*0.84u' pd='6.3u+1.68u' ps='6.3u+1.68u'");
      $spice_prim("+ as='6.3u*0.84u'");
      $spice_prim("M1 net20 pbias2 net17 inh_PmosB P  l=0.42u m=2 w=3.5u");
      $spice_prim("+ ad='3.5u*0.84u' pd='3.5u+1.68u' ps='3.5u+1.68u'");
      $spice_prim("+ as='3.5u*0.84u'");
      $spice_prim("M0 inh_vdd pbias1 net20 inh_PmosB P  m=2 l=0.42u");
      $spice_prim("+ w=3.5u ad='3.5u*0.84u' pd='3.5u+1.68u' ps='3.5u");
      $spice_prim("++1.68u' as='3.5u*0.84u'");
      $spice_prim("M5 outp nbias inh_gnd inh_NmosB N  w=1.26u l=1.68u");
      $spice_prim("+ ad='1.26u*0.84u' m=1 pd='1.26u+1.68u' ps='1.26u");
      $spice_prim("++1.68u' as='1.26u*0.84u'");
      $spice_prim("M4 outn nbias inh_gnd inh_NmosB N  l=1.68u w=1.26u");
      $spice_prim("+ ad='1.26u*0.84u' m=1 pd='1.26u+1.68u' ps='1.26u");
      $spice_prim("++1.68u' as='1.26u*0.84u'");
   end
//end Spice primitive instantiations


endmodule // delaycell 

