

module vco (inh_NmosB, inh_PmosB, inh_gnd, inh_vdd, net1, ibias, out, reset,
    vcontrol, net0);

//port section 
   inout inh_NmosB;
   inout inh_PmosB;
   inout inh_gnd;
   inout inh_vdd;
   inout net1;
   inout ibias;
   output out;
   input reset;
   input vcontrol;
   inout net0;
   electrical ground;

//end port section 

   vcobias  I0 (inh_NmosB, inh_PmosB, net1, vcontrol, net47, net46, net0);
   vcobias  I11 (inh_NmosB, inh_PmosB, net1, vcontrol, net24, net23, net0);
   delaycell  I1 (inh_NmosB, inh_PmosB, net1, phaseA, phaseAb, vcontrol,
    net35, net36, net47, net46, net0);
   delaycell  I2 (inh_NmosB, inh_PmosB, net1, net36, net35, vcontrol, net42,
    net43, net47, net46, net0);
   delaycell  I3 (inh_NmosB, inh_PmosB, net1, net43, net42, vcontrol, net49,
    net50, net47, net46, net0);
   delaycell  I6 (inh_NmosB, inh_PmosB, net1, net50, net49, vcontrol, net8,
    net15, net47, net46, net0);
   delaycell  I7 (inh_NmosB, inh_PmosB, net1, net57, net56, vcontrol,
    phaseA, phaseAb, net24, net23, net0);
   delaycell  I8 (inh_NmosB, inh_PmosB, net1, net64, net63, vcontrol, net56,
    net57, net24, net23, net0);
   delaycell  I9 (inh_NmosB, inh_PmosB, net1, net79, net80, vcontrol, net63,
    net64, net24, net23, net0);
   delaycell  I10 (inh_NmosB, inh_PmosB, net1, net15, net8, vcontrol, net80,
    net79, net24, net23, net0);
   levelrestore  I5 (inh_NmosB, inh_PmosB, net1, ibias, phaseAb, phaseA,
    out, net0);
   inv1  I15 (inh_NmosB, inh_PmosB, inh_gnd, reset, net12, inh_vdd);

//Spice primitive instantiations
      electrical inh_NmosB;
      electrical inh_PmosB;
      electrical net1;
      electrical reset;
      electrical net0;
   analog begin
      $spice_prim(".import vdd!");
      $spice_prim("M1 net0 net12 net15 inh_PmosB P  l=0.28u w='1.05U'");
      $spice_prim("+ ad='1.05U*0.84u' m=1 pd='1.05U+1.68u' ps='1.05U");
      $spice_prim("++1.68u' as='1.05U*0.84u'");
      $spice_prim("M3 net0 net0 net8 inh_PmosB P  l=0.28u w='1.05U'");
      $spice_prim("+ ad='1.05U*0.84u' m=1 pd='1.05U+1.68u' ps='1.05U");
      $spice_prim("++1.68u' as='1.05U*0.84u'");
      $spice_prim("M2 net15 net1 net1 inh_NmosB N  l=0.28u w=1.26u");
      $spice_prim("+ ad='1.26u*0.84u' m=1 pd='1.26u+1.68u' ps='1.26u");
      $spice_prim("++1.68u' as='1.26u*0.84u'");
      $spice_prim("M0 net8 reset net1 inh_NmosB N  w=1.26u l=0.28u");
      $spice_prim("+ ad='1.26u*0.84u' m=1 pd='1.26u+1.68u' ps='1.26u");
      $spice_prim("++1.68u' as='1.26u*0.84u'");
   end
//end Spice primitive instantiations


endmodule // vco 

