module tb ();

reg clk;
reg reset;
wire [3:0] counter_value;


initial clk = 0;
initial forever #5 clk = ~clk;

initial
  begin
         reset <= 1;
#1000    reset <= 0;




#30000   $stop;
  end

always @(counter_value)
    $display("counter value is now %x at time %t",counter_value, $time);

counter count1 (
                 .clk(clk),
                 .reset(reset),
                 .out(counter_value));


initial 
    $dumpfile("verilog.dmp");

initial
    $dumpvars;


endmodule