Index of /Share/Ebook/micro/DIGITAL/DOC
Name Last modified Size Description
![[PARENTDIR]](/__ovh_icons/back.gif)
Parent Directory -
![[ ]](/__ovh_icons/layout.gif)
00verilog.pdf 2017-06-18 18:57 137K
000L04.pdf 2017-06-18 18:58 309K
000Verilog-Modeling.pdf 2017-06-18 19:02 705K
000verilog_tutorial.pdf 2017-06-18 18:58 964K
0000Verilog-Intro.pdf 2017-06-18 19:01 867K
0000Xilinx_tutorial.pdf 2017-06-11 15:55 1.2M
![[ ]](/__ovh_icons/unknown.gif)
001.verilog-intro.ppt 2017-06-18 19:01 3.1M
02-Verilog2.pdf 2017-06-11 15:55 1.4M
02-VerilogFundametal..> 2017-06-11 15:55 1.0M
03-verilog-11.pdf 2017-06-11 19:09 355K
0470531088.pdf 2017-06-18 19:00 14M
06-VerilogII.pdf 2017-06-11 15:55 216K
07-SequentialVerilog..> 2017-06-11 15:55 582K
090908.ppt 2017-06-18 19:01 958K
13-misc-routing.pdf 2017-06-11 15:55 448K
15-Verilog and RTL.pdf 2017-06-18 18:57 2.2M
77_sm6_ena_ch1_intro..> 2017-06-11 15:55 241K
1996-CUG-presentatio..> 2017-06-11 15:55 171K
2013-SNUG-SV_Synthes..> 2017-06-11 15:55 312K
29105_0.pdf 2017-06-18 18:58 684K
1133628478_427915.pdf 2017-06-11 15:55 716K
AAAAverilog_tutorial..> 2017-06-18 18:58 964K
Advanced verilog cod..> 2017-06-11 15:55 6.5M
An Introduction to V..> 2017-06-11 15:55 320K
CH2 Modelisation de ..> 2017-06-11 15:55 2.6M
Chapter 6-Testbench.ppt 2017-06-11 15:55 2.1M
CombVerilog.pdf 2017-06-18 18:58 373K
CoursArchiLFL3S2.pdf 2017-06-11 15:55 1.1M
DFM04.PDF 2017-06-11 15:56 1.8M
DFM05.pdf 2017-06-11 15:56 4.1M
DFT.pdf 2017-06-11 15:56 190K
Digital%20Design%20L..> 2017-06-11 15:56 1.4M
FSM verilog.docx 2017-06-18 18:56 465K
HMEE107.pdf 2017-06-11 15:56 2.8M
HMEE327.pdf 2017-06-11 15:57 10M
Introduction à la C..> 2017-06-11 15:57 16M
L01.pdf 2017-06-11 15:57 312K
L03-Verilog-Design-E..> 2017-06-11 15:57 2.3M
L03.pdf 2017-06-11 15:57 344K
L04(1).pdf 2017-06-11 15:57 182K
L04.pdf 2017-06-11 15:57 182K
L05.pdf 2017-06-11 15:57 250K
L06-Physical-Design-..> 2017-06-11 15:57 972K
L06.pdf 2017-06-11 15:57 317K
Lab2AutoLayout2014.pdf 2017-06-11 19:09 2.0M
Lab2SimulationsTut20..> 2017-06-11 15:57 434K
Lecture-1-Introducti..> 2017-06-18 18:57 3.8M
Lecture2.pdf 2017-06-18 18:57 526K
Le langage VHDL Cour..> 2017-06-11 15:58 19M
PetervrlK.pdf 2017-06-11 15:57 128K
RTL Logic Synthesis ..> 2017-06-11 15:58 324K
Transparents_Int_Sys..> 2017-06-11 15:58 2.6M
VERILOG.docx 2017-06-11 15:59 25K
VHDL.pdf 2017-06-11 15:59 4.8M
VHDL_SS09_Teil10.pdf 2017-06-18 19:02 557K
VHDL for Logic Synth..> 2017-06-11 15:59 4.4M
Ver1Syn.pdf 2017-06-11 19:09 322K
Ver2Syn.pdf 2017-06-11 19:09 243K
Ver3Syn.pdf 2017-06-11 19:09 133K
Verilog-2012.pdf 2017-06-11 15:59 2.3M
Verilog-Intro.pdf 2017-06-11 15:59 818K
Verilog-Modeling.pdf 2017-06-11 15:59 1.1M
VerilogCombCkt.ppt 2017-06-18 19:02 1.0M
Verilog HDL (2).pdf 2017-06-11 15:59 243K
VerilogIntroduction_..> 2017-06-11 15:59 448K
VerilogPresent-v1.3.pdf 2017-06-18 18:58 1.4M
Verilog Slides.pdf 2017-06-18 19:01 294K
VerilogTutorial.pdf 2017-06-18 18:58 1.4M
Verilog_1.ppt 2017-06-18 19:01 215K
Verilog for Testing ..> 2017-06-18 18:57 682K
Verilog for synthesi..> 2017-06-18 18:57 2.6M
Verilog for synthesi..> 2017-06-18 18:57 3.0M
Verilog misc rev a.pdf 2017-06-18 18:57 3.8M
Verilog slides00.pdf 2017-06-18 19:02 352K
Verilog tutorial_lec..> 2017-06-11 15:59 433K
Verilog tutorial for..> 2017-06-18 19:01 1.1M
Week3_overheads.pdf 2017-06-11 15:59 429K
Yields.pdf 2017-06-11 16:00 320K
a100d36a5ee884c0c093..> 2017-06-18 19:01 121K
a431fdb8-721f-46d5-8..> 2017-06-11 15:55 5.2M
ae5df74f-0849-4c2c-8..> 2017-06-18 19:00 619K
b0cb488b113e6fcd56c1..> 2017-06-18 18:58 3.5M
bphy_verilog_hdl.pdf 2017-06-11 19:09 63K
chap14_lect13_scan.pdf 2017-06-11 15:55 292K
cmosvlsidesign_4e_Ap..> 2017-06-11 15:55 1.2M
cours9.pdf 2017-06-11 15:55 133K
dc.pdf 2017-06-18 18:58 2.9M
ddvh2.pdf 2017-06-11 15:56 1.8M
digital_testing.pdf 2017-06-11 15:56 870K
document(7).pdf 2017-06-11 15:56 403K
document(8).pdf 2017-06-11 15:56 372K
document(9).pdf 2017-06-11 15:56 553K
document(10).pdf 2017-06-11 15:56 270K
ee108a_nham_intro_to..> 2017-06-11 15:56 236K
ee460m_lab_manual.pdf 2017-06-11 19:09 2.3M
ele119_eprm_cours_tp..> 2017-06-11 15:56 6.9M
ele6306_chap8_JTAG.pdf 2017-06-11 15:56 282K
henry_masc_2004.pdf 2017-06-11 15:56 865K
intro_to_quartus2.pdf 2017-06-11 15:57 1.9M
intro_verilog_hdl.pdf 2017-06-11 15:57 1.8M
l02_verilog.pdf 2017-06-11 15:57 514K
l05_synthesis.pdf 2017-06-11 15:57 283K
l5.pdf 2017-06-18 18:57 549K
l15_testing.pdf 2017-06-11 15:57 279K
lecture2-verilog-130..> 2017-06-18 19:00 649K
lecture42014-1501050..> 2017-06-18 19:00 499K
pect1.pdf 2017-06-11 15:57 400K
pld_12.pdf 2017-06-18 18:57 616K
poly_1.pdf 2017-06-11 15:57 4.4M
poly_2.pdf 2017-06-11 15:58 6.9M
presentation2.pdf 2017-06-11 15:58 123K
rtl-verilog-navabi.pdf 2017-06-11 16:00 39M
synthesis-1409270411..> 2017-06-18 19:00 2.6M
synthesis-flow.pdf 2017-06-11 15:58 3.1M
tasksandfunctions-14..> 2017-06-18 19:00 162K
verilog(2).pdf 2017-06-11 15:59 237K
verilog(3).pdf 2017-06-11 15:59 170K
verilog-110729004421..> 2017-06-18 19:00 1.6M
verilog-140222044434..> 2017-06-18 19:00 865K
verilog-151225073511..> 2017-06-18 19:00 252K
verilog.ppt 2017-06-18 19:01 271K
verilog0000.pdf 2017-06-18 19:02 129K
verilog001.ppt 2017-06-18 19:01 154K
verilog1.pdf 2017-06-11 15:59 168K
verilogSlides.ppt 2017-06-18 19:01 616K
verilog_basics.ppt 2017-06-18 19:01 478K
verilog_lec.pdf 2017-06-18 19:01 73K
verilog_review.pdf 2017-06-18 19:01 465K
verilog_tutorial.pdf 2017-06-18 18:58 94K
verilog_tutorial1.ppt 2017-06-18 19:01 307K
verilog_tutorial3.ppt 2017-06-11 19:12 323K
veriloghdl-130130165..> 2017-06-18 19:00 1.0M
veriloghdl-140529090..> 2017-06-18 19:00 1.4M
verilogtutorial-1205..> 2017-06-18 19:00 1.7M
verilogtutorial-1407..> 2017-06-18 19:00 433K
verilogtutorial_1125..> 2017-06-18 19:01 682K
verilogver2-16012223..> 2017-06-18 19:00 1.5M