Index of /Share/Ebook/micro/DIGITAL/DOC

Icon  Name                    Last modified      Size  Description
[PARENTDIR] Parent Directory                             -   
[   ] VERILOG.docx            2017-06-11 15:59   25K  
[   ] bphy_verilog_hdl.pdf    2017-06-11 19:09   63K  
[   ] verilog_lec.pdf         2017-06-18 19:01   73K  
[   ] verilog_tutorial.pdf    2017-06-18 18:58   94K  
[   ] a100d36a5ee884c0c093..> 2017-06-18 19:01  121K  
[   ] presentation2.pdf       2017-06-11 15:58  123K  
[   ] PetervrlK.pdf           2017-06-11 15:57  128K  
[   ] verilog0000.pdf         2017-06-18 19:02  129K  
[   ] cours9.pdf              2017-06-11 15:55  133K  
[   ] Ver3Syn.pdf             2017-06-11 19:09  133K  
[   ] 00verilog.pdf           2017-06-18 18:57  137K  
[   ] verilog001.ppt          2017-06-18 19:01  154K  
[   ] tasksandfunctions-14..> 2017-06-18 19:00  162K  
[   ] verilog1.pdf            2017-06-11 15:59  168K  
[   ] verilog(3).pdf          2017-06-11 15:59  170K  
[   ] 1996-CUG-presentatio..> 2017-06-11 15:55  171K  
[   ] L04(1).pdf              2017-06-11 15:57  182K  
[   ] L04.pdf                 2017-06-11 15:57  182K  
[   ] DFT.pdf                 2017-06-11 15:56  190K  
[   ] Verilog_1.ppt           2017-06-18 19:01  215K  
[   ] 06-VerilogII.pdf        2017-06-11 15:55  216K  
[   ] ee108a_nham_intro_to..> 2017-06-11 15:56  236K  
[   ] verilog(2).pdf          2017-06-11 15:59  237K  
[   ] 77_sm6_ena_ch1_intro..> 2017-06-11 15:55  241K  
[   ] Ver2Syn.pdf             2017-06-11 19:09  243K  
[   ] Verilog HDL (2).pdf     2017-06-11 15:59  243K  
[   ] L05.pdf                 2017-06-11 15:57  250K  
[   ] verilog-151225073511..> 2017-06-18 19:00  252K  
[   ] document(10).pdf        2017-06-11 15:56  270K  
[   ] verilog.ppt             2017-06-18 19:01  271K  
[   ] l15_testing.pdf         2017-06-11 15:57  279K  
[   ] ele6306_chap8_JTAG.pdf  2017-06-11 15:56  282K  
[   ] l05_synthesis.pdf       2017-06-11 15:57  283K  
[   ] chap14_lect13_scan.pdf  2017-06-11 15:55  292K  
[   ] Verilog Slides.pdf      2017-06-18 19:01  294K  
[   ] verilog_tutorial1.ppt   2017-06-18 19:01  307K  
[   ] 000L04.pdf              2017-06-18 18:58  309K  
[   ] L01.pdf                 2017-06-11 15:57  312K  
[   ] 2013-SNUG-SV_Synthes..> 2017-06-11 15:55  312K  
[   ] L06.pdf                 2017-06-11 15:57  317K  
[   ] An Introduction to V..> 2017-06-11 15:55  320K  
[   ] Yields.pdf              2017-06-11 16:00  320K  
[   ] Ver1Syn.pdf             2017-06-11 19:09  322K  
[   ] verilog_tutorial3.ppt   2017-06-11 19:12  323K  
[   ] RTL Logic Synthesis ..> 2017-06-11 15:58  324K  
[   ] L03.pdf                 2017-06-11 15:57  344K  
[   ] Verilog slides00.pdf    2017-06-18 19:02  352K  
[   ] 03-verilog-11.pdf       2017-06-11 19:09  355K  
[   ] document(8).pdf         2017-06-11 15:56  372K  
[   ] CombVerilog.pdf         2017-06-18 18:58  373K  
[   ] pect1.pdf               2017-06-11 15:57  400K  
[   ] document(7).pdf         2017-06-11 15:56  403K  
[   ] Week3_overheads.pdf     2017-06-11 15:59  429K  
[   ] Verilog tutorial_lec..> 2017-06-11 15:59  433K  
[   ] verilogtutorial-1407..> 2017-06-18 19:00  433K  
[   ] Lab2SimulationsTut20..> 2017-06-11 15:57  434K  
[   ] VerilogIntroduction_..> 2017-06-11 15:59  448K  
[   ] 13-misc-routing.pdf     2017-06-11 15:55  448K  
[   ] verilog_review.pdf      2017-06-18 19:01  465K  
[   ] FSM verilog.docx        2017-06-18 18:56  465K  
[   ] verilog_basics.ppt      2017-06-18 19:01  478K  
[   ] lecture42014-1501050..> 2017-06-18 19:00  499K  
[   ] l02_verilog.pdf         2017-06-11 15:57  514K  
[   ] Lecture2.pdf            2017-06-18 18:57  526K  
[   ] l5.pdf                  2017-06-18 18:57  549K  
[   ] document(9).pdf         2017-06-11 15:56  553K  
[   ] VHDL_SS09_Teil10.pdf    2017-06-18 19:02  557K  
[   ] 07-SequentialVerilog..> 2017-06-11 15:55  582K  
[   ] verilogSlides.ppt       2017-06-18 19:01  616K  
[   ] pld_12.pdf              2017-06-18 18:57  616K  
[   ] ae5df74f-0849-4c2c-8..> 2017-06-18 19:00  619K  
[   ] lecture2-verilog-130..> 2017-06-18 19:00  649K  
[   ] verilogtutorial_1125..> 2017-06-18 19:01  682K  
[   ] Verilog for Testing ..> 2017-06-18 18:57  682K  
[   ] 29105_0.pdf             2017-06-18 18:58  684K  
[   ] 000Verilog-Modeling.pdf 2017-06-18 19:02  705K  
[   ] 1133628478_427915.pdf   2017-06-11 15:55  716K  
[   ] Verilog-Intro.pdf       2017-06-11 15:59  818K  
[   ] henry_masc_2004.pdf     2017-06-11 15:56  865K  
[   ] verilog-140222044434..> 2017-06-18 19:00  865K  
[   ] 0000Verilog-Intro.pdf   2017-06-18 19:01  867K  
[   ] digital_testing.pdf     2017-06-11 15:56  870K  
[   ] 090908.ppt              2017-06-18 19:01  958K  
[   ] 000verilog_tutorial.pdf 2017-06-18 18:58  964K  
[   ] AAAAverilog_tutorial..> 2017-06-18 18:58  964K  
[   ] L06-Physical-Design-..> 2017-06-11 15:57  972K  
[   ] veriloghdl-130130165..> 2017-06-18 19:00  1.0M  
[   ] 02-VerilogFundametal..> 2017-06-11 15:55  1.0M  
[   ] VerilogCombCkt.ppt      2017-06-18 19:02  1.0M  
[   ] Verilog-Modeling.pdf    2017-06-11 15:59  1.1M  
[   ] Verilog tutorial for..> 2017-06-18 19:01  1.1M  
[   ] CoursArchiLFL3S2.pdf    2017-06-11 15:55  1.1M  
[   ] cmosvlsidesign_4e_Ap..> 2017-06-11 15:55  1.2M  
[   ] 0000Xilinx_tutorial.pdf 2017-06-11 15:55  1.2M  
[   ] VerilogPresent-v1.3.pdf 2017-06-18 18:58  1.4M  
[   ] Digital%20Design%20L..> 2017-06-11 15:56  1.4M  
[   ] 02-Verilog2.pdf         2017-06-11 15:55  1.4M  
[   ] VerilogTutorial.pdf     2017-06-18 18:58  1.4M  
[   ] veriloghdl-140529090..> 2017-06-18 19:00  1.4M  
[   ] verilogver2-16012223..> 2017-06-18 19:00  1.5M  
[   ] verilog-110729004421..> 2017-06-18 19:00  1.6M  
[   ] verilogtutorial-1205..> 2017-06-18 19:00  1.7M  
[   ] ddvh2.pdf               2017-06-11 15:56  1.8M  
[   ] DFM04.PDF               2017-06-11 15:56  1.8M  
[   ] intro_verilog_hdl.pdf   2017-06-11 15:57  1.8M  
[   ] intro_to_quartus2.pdf   2017-06-11 15:57  1.9M  
[   ] Lab2AutoLayout2014.pdf  2017-06-11 19:09  2.0M  
[   ] Chapter 6-Testbench.ppt 2017-06-11 15:55  2.1M  
[   ] 15-Verilog and RTL.pdf  2017-06-18 18:57  2.2M  
[   ] L03-Verilog-Design-E..> 2017-06-11 15:57  2.3M  
[   ] ee460m_lab_manual.pdf   2017-06-11 19:09  2.3M  
[   ] Verilog-2012.pdf        2017-06-11 15:59  2.3M  
[   ] Verilog for synthesi..> 2017-06-18 18:57  2.6M  
[   ] CH2 Modelisation de ..> 2017-06-11 15:55  2.6M  
[   ] Transparents_Int_Sys..> 2017-06-11 15:58  2.6M  
[   ] synthesis-1409270411..> 2017-06-18 19:00  2.6M  
[   ] HMEE107.pdf             2017-06-11 15:56  2.8M  
[   ] dc.pdf                  2017-06-18 18:58  2.9M  
[   ] Verilog for synthesi..> 2017-06-18 18:57  3.0M  
[   ] 001.verilog-intro.ppt   2017-06-18 19:01  3.1M  
[   ] synthesis-flow.pdf      2017-06-11 15:58  3.1M  
[   ] b0cb488b113e6fcd56c1..> 2017-06-18 18:58  3.5M  
[   ] Verilog misc rev a.pdf  2017-06-18 18:57  3.8M  
[   ] Lecture-1-Introducti..> 2017-06-18 18:57  3.8M  
[   ] DFM05.pdf               2017-06-11 15:56  4.1M  
[   ] VHDL for Logic Synth..> 2017-06-11 15:59  4.4M  
[   ] poly_1.pdf              2017-06-11 15:57  4.4M  
[   ] VHDL.pdf                2017-06-11 15:59  4.8M  
[   ] a431fdb8-721f-46d5-8..> 2017-06-11 15:55  5.2M  
[   ] Advanced verilog cod..> 2017-06-11 15:55  6.5M  
[   ] poly_2.pdf              2017-06-11 15:58  6.9M  
[   ] ele119_eprm_cours_tp..> 2017-06-11 15:56  6.9M  
[   ] HMEE327.pdf             2017-06-11 15:57   10M  
[   ] 0470531088.pdf          2017-06-18 19:00   14M  
[   ] Introduction à la C..> 2017-06-11 15:57   16M  
[   ] Le langage VHDL Cour..> 2017-06-11 15:58   19M  
[   ] rtl-verilog-navabi.pdf  2017-06-11 16:00   39M