Index of /XTRAIL/WORKAREA/HDL

Icon  Name                    Last modified      Size  Description
[PARENTDIR] Parent Directory                             -   
[   ] 00verilog_faq.pdf       2017-06-08 23:36   17M  
[   ] 01VerilogHDL.pdf        2017-07-23 19:06  1.3M  
[   ] 0123695279 - (2007) ..> 2017-06-08 23:27  2.0M  
[   ] 0132774208.pdf          2017-06-08 23:31  3.0M  
[   ] 0134516753 - (1996) ..> 2017-06-08 23:31   11M  
[   ] 0470054379 - (2007) ..> 2017-06-08 23:28  6.9M  
[   ] 052182866X - (2004) ..> 2017-06-08 23:26  1.1M  
[   ] 1770d6c9a3a9e41cfa86..> 2017-06-08 23:31  2.9M  
[   ] 101104447-FSM-Based-..> 2017-06-08 23:30  2.7M  
[   ] 1118841093.pdf          2017-06-08 23:37   21M  
[   ] 1133628478_427915.pdf   2017-06-05 19:21  716K  
[   ] 3319047884VLSI.pdf      2017-07-23 19:06   15M  
[   ] 8132227891.pdf          2017-06-05 19:23   56M  
[   ] AEV2.pdf                2015-06-21 18:35  906K  
[   ] An Introduction to V..> 2015-06-21 18:39  320K  
[   ] CoursArchiLFL3S2.pdf    2015-06-21 18:37  1.1M  
[   ] Course_verilog_tutor..> 2015-06-21 18:32  876K  
[   ] Design Through Veril..> 2017-06-05 19:19  2.2M  
[   ] Digital_Design_-_Fif..> 2017-06-05 19:20  3.0M  
[DIR] Doc Realmont/           2019-03-10 10:07    -   
[   ] Fundamentals of Digi..> 2017-06-05 19:21  5.6M  
[   ] PSI-Skill-full.pdf      2017-06-08 23:29  1.0M  
[   ] SNUG10_fork_slides.pdf  2017-07-23 19:06  1.1M  
[   ] Simulation NC Verilo..> 2015-06-21 18:58  1.0M  
[   ] Stephen Brown and Zv..> 2015-06-21 18:41  6.7M  
[   ] SystemVerilog Interf..> 2017-07-23 19:06  1.6M  
[   ] SystemVerilog_for_Ve..> 2017-07-23 19:06  2.5M  
[   ] SystemVerilog_verifl..> 2017-07-23 19:06  274K  
[   ] VERILOG.docx            2015-06-21 19:00   25K  
[   ] VHDL.pdf                2015-06-21 18:36  4.8M  
[   ] Verilog HDL (2).pdf     2017-06-05 19:21  243K  
[   ] Verilog HDL - Samir ..> 2017-06-05 19:20   11M  
[   ] Verilog HDL Synthesi..> 2017-06-05 19:21  5.1M  
[   ] Verilog Rise edge de..> 2017-12-04 23:26  383K  
[   ] Verilog and SystemVe..> 2018-04-23 23:46   12M  
[   ] Verilog tutorial_lec..> 2015-06-21 18:33  433K  
[   ] Writing testbenches ..> 2017-07-23 19:05  1.9M  
[   ] Xilinx_tutorial.pdf     2017-06-05 19:22  1.2M  
[   ] b0cb488b113e6fcd56c1..> 2017-06-05 19:20  3.5M  
[   ] book_systemverilog_f..> 2017-07-23 19:06  1.4M  
[   ] cmosvlsidesign_4e_Ap..> 2017-06-05 19:23  1.2M  
[TXT] code verilog.txt        2017-12-04 23:26  5.0K  
[IMG] compass.png             2017-06-05 19:21  1.2K  
[IMG] compass01.png           2017-06-05 19:21  2.1K  
[IMG] compass_good.png        2017-06-05 19:21  2.2K  
[   ] ddvh2.pdf               2017-06-05 19:19  1.8M  
[   ] e-1439811245.pdf        2017-06-05 19:22   16M  
[   ] ee108a_nham_intro_to..> 2017-06-05 19:20  236K  
[   ] intro_to_quartus2.pdf   2017-06-05 19:21  1.9M  
[   ] intro_verilog_hdl.pdf   2017-06-05 19:21  1.8M  
[   ] l02_verilog.pdf         2015-06-21 18:38  514K  
[IMG] map.png                 2017-06-05 19:21  2.0K  
[IMG] maps-and-flags01.png    2017-06-05 19:21  3.1K  
[   ] ourdev_212115.pdf       2017-06-05 19:20  5.1M  
[   ] ourdev_585395BQ8J9A.pdf 2017-06-05 19:19  2.3M  
[   ] poly_1.pdf              2015-06-21 18:37  4.4M  
[   ] poly_2.pdf              2015-06-21 18:38  6.9M  
[   ] presentation2.pdf       2015-06-21 18:34  123K  
[   ] rtl-verilog-navabi.pdf  2015-06-21 18:49   39M  
[IMG] safari.png              2017-06-05 19:21  1.6K  
[   ] synthesis-flow.pdf      2017-06-05 19:19  3.1M  
[   ] synver.pdf              2015-06-21 18:39  2.2M  
[   ] tutoriel_verilog.docx   2015-06-21 19:02   95K  
[   ] verilog(3).pdf          2015-06-21 18:37  170K  
[   ] verilog-a4.pdf          2017-07-23 19:06  481K  
[   ] verilog_2001_ref_gui..> 2017-06-05 19:21  269K  
[   ] verilog_faq.pdf         2017-06-05 19:19   17M  
[   ] verilog_tutorial.pdf    2017-06-05 19:19  876K  
[   ] yosys_manual.pdf        2017-06-05 19:20  1.8M